Stir together 200,000 logic cells and 500-MHz performance, and you get the Integrated Software Environment (ISE) from Xilinx. Following on its recent announcement of the Virtex-4 family of platform FPGAs, the company rolled out the 6.3i release of its ISE design suite, which takes advantage of the Virtex-4 architecture.
New to version 6.3i of ISE is support for the Linux Red Hat Enterprise 3.0 operating system. There's also a variety of enhancements intended to boost productivity while supporting the 100+ new features available in Virtex-4 devices.
Architecture wizards in ISE enable rapid configuration of Virtex-4 devices, including a ChipSync wizard for fast and accurate source synchronous-interface designs. The XtremeDSP Slice wizard makes easier work of designs targeted at the Virtex-4 XtremeDSP device. Other wizards handle serial I/Os up to 11.1 Gbits/s and internal clock configuration.
The Pin and Area Constraints Editor (PACE) tool delivers pin management and logic-area floorplanning. PACE includes engineering-rule checks for simultaneous-switching outputs to help identify potential ground-bounce problems.
The PlanAhead hierarchical floorplanner is available as an option. PlanAhead helps cut down on place-and-route time and can result in fewer iterations. It supports design reuse and IP optimization earlier in the design cycle and at higher levels of abstraction.
Also optional is ChipScope Pro 6.3i, a real-time hardware debugger that now also supports Red Hat Enterprise 3.0. The tool includes new storage qualification for more efficient use of trace debug memory.
ISE v6.3i handles Virtex-4 and Spartan-3 FPGAs and CoolRunner-II complex programmable logic devices. All ISE configurations are available now with prices ranging from $695 to $2495. A free downloadable ISE WebPack 6.3i is available, as is a free 60-day evaluation version of ISE Foundation. ChipScope Pro costs $695, and Plan-Ahead goes for $15,000.