Electronic Design

Processor Combines Scalable DSP With RISC Control Code

The high-performance OneDSP scalable processor architecture is designed specifically to provide the processing power next-generation applications require. It's the first processor to combine scalable, high-performance DSP with general-purpose RISC control code in a true, single core. This tool delivers scalable DSP performance by applying novel very-long-instruction-word (VLIW) clustering techniques.

OneDSP is deployed in a family of synthesizable cores, the first of which is the SRA328. Exploiting instruction-level parallelism, the OneDSP architecture provides up to 32 execution-unit clusters to be implemented by the licensee with either 32- or 64-bit data paths. OneDSP will scale from 400 MMACs (with only the master cluster deployed) to 25,600 MMACs with 32 clusters at 200 MHz. DSP features include operand support for integer, fractional, floating point, boolean, and complex data types in 8-, 16-, 32-, 44-, and 88-bit formats.

For pricing and availability information, contact the company.

Siroyan Limited
+44 (0) 118 949-7028; www.siroyan.com

TAGS: Digital ICs
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