Most processors run a single instruction set. But the ARM1026EJ-S implements four in hardware, including 32-bit ARM instructions, 16-bit ARM Thumb instructions, ARM DSP instructions, and Java bytecodes. Thumb instructions are more compact than the 32-bit ARM instructions, but they run just as fast, and there is no context switch.
ARM uses its Jazelle hardware acceleration technology to support Java. ARM processors typically run multiple applications. The plethora of instruction sets lets designers choose the best one to support a particular application. The VFP10 floating-point coprocessor can also be included in a system. It adds single-instruction, multiple-data (SIMD) vector instruction support.
The processor uses a dual 64-bit AMBA AHB bus, making system-on-a-chip design easier when AHB bus-compliant peripherals are included. De-signers can boost debugging by including the ETM10 enhanced trace macrocell. This provides a nonintrusive, real-time trace facility that works with ARM debuggers.
The ARM1026EJ-S is available now as soft IP. Hard IP is available upon request. The synthesizable core permits configuration of memory management units, caches and protection support, and selection of the optional floating-point system. The 325-MHz version uses 0.13-µm technology.
ARM Inc., www.arm.com; (408) 579-2200.