For a decade now, mainstream complex ASIC design and verification has been done at one level of abstraction. Logic is captured, tests are generated, simulations are analyzed, and IP is delivered at the register-transfer level (RTL). As we enter the era of ESL methodologies, one thing is clear: The EDA front-end will not remain this homogeneous. ESL is a mixed-abstraction methodology, and there are several reasons why:
1. ESL synthesis tools have multiple entry points:
Every ESL synthesis tool seems to have its own level of abstraction as its entry point. There are tools for mathematical algorithms, DSP functions, embedded CPU microcode, un-timed transaction-level models (TLMs), approximately timed TLMs, cycle-callable TLMs, and non-HDL cycle-accurate models. The only commonality among them is their output—RTL, of course.
Many of these approaches have proven their value. Major SoC developments will likely use several of them to address different sub-segments of the design.
2. There are hard requirements for multiple transaction levels:
The design disciplines of application software, device drivers, SoC architectures, system validation, and chip verification have different requirements for model timing and behavior accuracy. As a result, three levels of modeling abstraction have emerged above RTL. These are Programmer's View (PV), Programmer's View with Timing (PVT) and Cycle Callable (CC). Most complex ASIC developments will use at least two of these, and the most challenging will use all three as well as RTL.
3. An enormous body of proven IP is represented at RTL:
The majority of logic in most complex ASICs or ASSPs is reused from existing designs. Today, almost all of this is represented at RTL only. It is unlikely that a tool to automatically convert RTL into the varying transaction levels will appear. Only the blockbusting, must-have star IP will justify the effort of creating the required TLMs or abstract testbenches.
Tools that automatically convert HDL-based RTL into reduced-variable SystemC or C++ already exist. Although considerably faster than standard HDL, these models are still effectively at RTL.
4. The lowest common denominator will still be RTL:
In the emerging ESL methodology, the first time that the whole design will exist at one level of abstraction is when 100% of the RTL is complete. Obviously too late, this results in an environment that is too slow for software development and comprehensive system validation and chip verification. We have been here for years.
The true goals of ESL can only be met by mixing levels of abstraction. The aim of ESL has always been to reduce the effort and time required to produce complete silicon-based systems. This means automating design, accelerating validation and verification, and facilitating parallel hardware and software development.
The original ESL visionaries did envision a homogeneous, very abstract front-end complemented by comprehensive ESL-to-gate-level synthesis tools. In reality, the front end is, and will be, far from homogeneous, and the synthesis tools are each addressing only small parts of the system. The RTL-to-GDSII flow continues to evolve, making it unforeseeable that RTL will ever be bypassed. The only way to create representations of complete designs early enough to affect architectural decisions and fast enough for software development and exhaustive verification is to mix and match models from different levels of abstraction.