Electronic Design

Reconfigurable SoCs

Platform-based SoC designs are one way to get an SoC without starting from scratch. Often, there's some compromise when taking this approach because the standard components in the platform might not be exactly what the designer wants.

Tensilica's Xtensa is an example of a platform-based design. The architecture consists of a configurable 200-MHz, 32-bit architecture with an optional DSP. The Tensilica Xtensa Processor Generator supports the addition of designer-defined instructions using Tensilica Instruction Extension Language (TIE).

Reconfigurable SoCs are another alternative. The figure shows the similarity between the two designs. In platform-based solutions, standard components like a microprocessor core make up a significant portion of the SoC. The custom IP provides further functionality.

The reconfigurable SoC provides the same kind of custom IP support except that the IP is implemented using a reconfigurable matrix. The software must set up the hardware before it can be used. But from that point on, the platform-based SoC software and reconfigurable SoC software will be very similar, assuming that the microprocessor core is the same or similar and the functionality of the IP has the same characteristics.

There are a number of reconfigurable SoCs on the market employing different microprocessor cores and different types of reconfigurable matrices. Atmel's AT94K family of Field Programmable System Level Integrated Circuit (FPSLIC) chips are based on a 30-MIPS AVR 8-bit RISC microprocessor core. They have numerous fixed microcontroller peripherals and a total of 36 kbytes of program and data SRAM. The FPSLIC reconfigurable matrix is based on Atmel's 10- through 40-kgate FPGAs. This combination makes it an ideal replacement for Atmel customers already using the AVR microprocessor core and an FPGA in a two- or three-chip solution. Additionally, it's an ideal combination for new customers that need both reconfigurability as well as the power provided by the FPSLIC design.

Chameleon Systems' CS2000 Reconfigurable Communications Processor (RCP) is another reconfigurable SoC for network processor chores (see "Scalable, Reconfigurable Processor Adjusts Logic For Top Performance," Electronic Design, May 15, p. 66). Its RISC processor is based on the popular ARC core from ARC Cores Ltd.

The CS2112, the first of the CS2000 series, has a reconfigurable component based around four slices with three tiles per slice. This translates into 84 datapath units, 24 multipliers, and 48 local-store memories—totalling 196 kbits that a designer can customize.

Just because the reconfigurable SoCs are available off the shelf, it doesn't mean that co-design and co-verification tools aren't necessary. In fact, they are key to taking advantage of the reconfiguration capabilities of the chips. Atmel provides state-of-the-art tools that allow concurrent hardware and software development.

Chameleon's C~SIDE development tools enable designers to create new configurations for the CS2000 RCP. C~SIDE includes ChipSim, a full chip simulator. This lets designers test both the configuration and the software.

Reconfigurable SoC designs have two features that set them apart from other SoC designs. The first is the ability to change the hardware functionality simply by altering the code that performs system initialization.

The second item is an offshoot of this. The reconfiguration can occur an arbitrary number of times after the hardware is initialized. A number of applications can utilize this feature. For instance, a multimedia player could configure a hardware codec for the type of data stream being used, such as MPEG1 or MPEG2. A similar mode would be used by a virtual private network (VPN) client or server that can use different encryption methods implemented in hardware.

The main downside of using a standard reconfigurable SoC is cost compared to a custom SoC. The tradeoff will be related to the number of chips that will be shipped and any advantage for getting the product to market sooner. Custom designs typically have large up-front development costs, but low individual chip costs. Reconfigurable SoCs have a comparatively small up-front cost, but usually they're more expensive per chip.

TAGS: Digital ICs
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