Wireless Systems Design

RF And Digital Tests Unite Against BER

The novel integration of the RF and digital-verification domains adds simulation and test capabilities to traditional logic analyzers.

In today's wireless-receiver architecture, an evolving trend places the digital-signal-processor (DSP) subsystem closer to the radio-frequency (RF) antenna. This trend highlights a need for innovative RF/digital-verification solutions. Many receivers now include an RF downconverter as a front end and at least one analog-to-digital converter (ADC) on the back end. These receivers can pose design and verification challenges for RF system engineers. The system engineers need to partition radio-frequency requirements and then verify RF performance parameters. Critical RF-receiver performance metrics, such as coded bit error rate (BER), can present significant challenges for RF designers. After all, the receiver input is an analog RF signal. But the output is in a completely different signal format—namely, digital bits.

In the past, logic analyzers have been primarily used for digital analysis. Typically, these instruments haven't been part of the RF system engineer's verification suite. This article will demonstrate a unique method of extending the logic analyzer's domain into the RF system engineer's verification space. The approach combines the logic-analyzer and RF-design-simulation solutions. The resulting combined approach will enable coded-BER measurements to be performed on RF mixed-signal hardware. By providing baseband post-processing functionality, this combined solution can handle coded-BER and coded-packet-error-rate (PER) measurements for signal formats like 3GPP W-CDMA and wireless local-area network (WLAN).

In addition, RF measurements like error vector magnitude (EVM) can be introduced into the digital domain (post-ADC). Simply apply Vector Signal Analysis (VSA) post-processing to the measured digital signal. Such post-processing, which is available in the simulation design environment, is accomplished once the data has been read from the logic analyzer into the simulation environment. Post-processing can help the RF system engineer partition RF performance requirements across the analog-to-digital boundary in a mixed-signal receiver. This approach also provides a methodology for verifying the RF performance even after the signal has been digitized with the ADC(s).

RF receivers may include one or more analog-to-digital converters in order to digitize intermediate-frequency (IF) or analog I and Q signals (FIG. 1). There are three different receiver architectures:

  1. Superheterodyne (RF-IF-analog-DSP)
  2. Direct conversion (RF-analog-DSP)
  3. Digital IF (RF-IF-DSP)

All three of these architectures also are known as topologies. They employ at least one ADC at some stage along the receiver chain before baseband post-processing is applied.

Receiver topologies like the ones listed above may present a challenge to the RF system engineer. Although the input signal to the receiver is analog RF, the output signal(s) is digital. Traditional verification methodologies use RF signal generators and vector signal analyzers. These methodologies may not suffice for end-to-end verification on mixed-signal-receiver topologies (once the IF or I and Q signals have been digitized with an ADC). Yet the RF system specifications must still be partitioned. In addition, the resulting RF performance of the entire mixed-signal receiver still has to be verified. These issues highlight the need for a new mixed-signal verification—or combined-solutions—approach.

Conceptually, such an approach starts by generating a simulated signal. That signal is then downloaded to a signal-source arbitrary waveform generator. The generator, in turn, creates the physical RF or IF test signal in the device-under-test (FIG. 2). The device-under-test (DUT) could be a receiver with ADCs. It outputs a digitized signal(s) that is measured and captured with the logic analyzer. The logic analyzer then captures the digital data synchronously with the ADC's sampling clock. Next, the logic analyzer's memory is read into the simulation design environment. To perform the BER or PER measurement, the memory is post-processed by the simulation solution's baseband receiver.

In this approach, it's critical to maximize the amount of data that's passed through the DUT in order to achieve a statistically meaningful BER/PER-measurement result. The time synchronization of the data, which was created by the simulation solution and measured by the logic analyzer, is equally important. These issues will be addressed and discussed in the following sections of this article.

The RF/baseband partition in a receiver can be a potentially difficult challenge for the RF system engineer. The ADC(s) may be part of the RF section of a receiver system. But the baseband hardware/software de-coding functionality that's required for a coded-BER/PER measurement may not be part of that section. It may therefore be difficult to verify the coded-BER/PER performance of an RF receiver independently of the baseband section. If integration problems are identified late in the hardware-testing phase, this issue may result in testing delays and increased costs.

When addressing this verification challenge, it may help to use simulation blocks to represent the missing baseband functionality that's required to perform the coded-BER/PER measurement. This approach also can help to mitigate RF/baseband integration risks. It allows the RF testing to be performed independent of the baseband section. One application of such an approach can be illustrated with the 3GPP W-CDMA uplink coding structure (FIG. 3).

For the dedicated-traffic-channel (DTCH), the 244 bits are for a 12.2-kbps reference channel for one 20-ms transmission time interval (TTI). Cyclical-redundancy-check (CRC) bits are added to the DTCH bits along with tail bits. Next, rate-one-third convolutional coding is performed and the bits are interleaved. The 20-ms TTI are then frame-segmented into 10-ms frames. To achieve the desired bit rate, bits are inserted/punctured.

Transport-channel multiplexing is then performed with the dedicated control channel (DCCH). Next, a second interleaving of the bits is performed. At this point, the dedicated physical data channel (DPDCH) is spread with a 3.84-mega-chip-per-second (MCps) orthogonal-variable-spread-factor (OVSF) code for the I waveform. For the Q waveform, the dedicated physical control channel (DPCCH) is spread with a 3.84-MCps OVSF code. Finally, a scrambling code is applied to the I and Q waveforms. Later, the waveforms are root-raised-cosine filtered and modulated onto an IF or RF carrier.

This example of a 3GPP W-CDMA uplink coding structure shows that a significant amount of coding is performed on the transmitted signal. The coding is applied in simulation before the simulated signal is downloaded to the signal-generator arbitrary waveform generator for this application.

On the receiver side, the coding that's applied to the transmitted signal is addressed in reverse. It can therefore recover the original DTCH bits that were transmitted. This step is necessary to perform a coded-BER measurement. Consequently, the baseband functionality is applied to the DUT's output using a simulated baseband receiver. This step occurs after the DUT output data has been captured by the logic analyzer and read into the simulation solution. Functionally, this approach can be understood by looking into the lower-level hierarchy of the baseband-receiver simulation model.

The significance of the coding structure on the RF BER/PER performance itself isn't discussed in detail in this article. However, it is discussed in other references for W-CDMA system design and verification or WLAN-receiver testing.

For the test setup, a laptop PC with the simulation solution is used to create the W-CDMA modulated IF test signal (FIG. 4). This test approach is implemented by downloading the simulated signal to the signal source's arbitrary waveform generator using a LAN connection. For this test setup, the signal source's arbitrary waveform generator will accept up to 32 Msamples of simulation data. Yet other options are available for downloading up to 64 Msamples of simulation data.

The W-CDMA-modulated 10-MHz signal is digitized with a 14-b analog-to-digital converter. Using a second signal generator, that ADC is clocked at 30.72 MHz. The 30.72 MHz represents an 8X oversampling of the 3.84-MCps W-CDMA waveforms. The logic analyzer captures the 14-b digital output of the analog-to-digital board. The measured data in the logic analyzer's memory is retrieved by the simulation solution using a LAN connection. Because of a significant speed advantage, which is useful for BER/PER applications, a binary-memory-based read of the logic-analyzer data is used instead of an ASCII file transfer. The logic analyzer is capable of storing up to 32 Msamples of data in memory for each channel in state mode. In that mode, the logic analyzer is clocked synchronously with the target device's clock.

As mentioned earlier, one of the challenges with this type of application is time-synchronizing the data. The goal is to take the data that was created by the simulation solution and synchronize it with the measured data that was captured with the logic analyzer. To address this challenge, an "event marker" is enabled on the signal source. This marker triggers a pulse on the rear-panel BNC connector when the first point of the arbitrary waveform generator begins. (The first point of the arbitrary waveform generator is downloaded from the simulation solution.)

To synchronize the logic-analyzer measurement with the start of the arbitrary waveform generator, the signal source's event-marker output is connected to the logic-analyzer arm input. The logic analyzer is then configured with a special setup file, which will trigger its measurement on the occurrence of the signal-source event marker. This measurement, in turn, will fill the logic analyzer's memory with the measured data. Even with this synchronization, however, a small, residual physical delay may exist. This delay would need to be removed in order to perform the BER/PER measurement. The removal of small residual delays can be addressed in simulation prior to performing the BER/PER measurement. For the examples shown in this article, the delay removal was performed in simulation using the W-CDMA and WLAN baseband receivers.

For the test results, the arbitrary-waveform-generator capacity limit was kept to 80 frames of data. It provided a snapshot of the 3GPP W-CDMA coded-BER results after several test plots had been created. The first one took the magnitude of the waveforms that were downloaded from the simulation solution to the signal generator. It then compared them to the magnitude of the waveforms that were read from the logic analyzer back into the simulation environment as a function of time.

Another set of test plots consisted of the reference bits that were generated by the simulation solution. Those bits were overlaid with the bits that were recovered from the DUT output. The logic-analyzer unified solution was used as a function of the number of bits. Settings for these test plots included the physical BER (no coding) as a function of 10-ms radio frames and the coded BER as a function of 20-ms TTI. At this RF power level, no difference was observed between the coded-BER and uncoded-physical-BER results. Keep in mind that the signal level was significantly higher than the receiver's sensitivity level.

A similar test setup and procedure was performed for IEEE 802.11a. Here, a WLAN simulation signal source and receiver were used. The frequencies were changed for the test-signal sources. The DUT that was used was the same one that was utilized in the W-CDMA case. The resulting test plot could be used to compare the packet-error-rate curve as a function of amplitude into the DUT.

Once the measured digital data from the DUT is read into the simulation solution, it can be post-processed with the RF-simulation measurement capability that's available in the simulation environment. Consider an example in which the vector-signal-analysis (VSA) simulation-measurement software is used to post-process the digital data that was measured with the logic analyzer (FIG. 5). The digitized WLAN data is being analyzed at the ADC's output using VSA simulation-measurement software. All of the pertinent data can be examined including the sampled constellation, IF spectrum, error vector magnitude (EVM), and EVM-versus-subcarrier values. Although they weren't shown in this article, similar measurements have been performed for W-CDMA including code-domain power.

The flexibility of performing RF analysis on digitized measured data opens up a new domain for the RF system engineer. Using a logic analyzer, he or she can verify RF performance after the ADC(s). The possibilities include analyzing EVM versus clock jitter, analog-to-digital quantization error, and other non-linearities versus EVM.

This article has attempted to demonstrate a novel method of integrating the RF and digital-verification domains. This approach combines simulation and test solutions to create innovative new solutions that couldn't exist with either simulation or test alone. Simulation was used to effectively extend the logic analyzer's capability. It provided the baseband functionality that's needed to perform coded-BER/PER measurements on mixed RF/digital systems. The examples that were presented revolved around measurements that were performed with an ADC. Yet other possibilities could include RF/digital-receiver hardware or even a combination of RF/digital hardware and RF/baseband simulation models. They could be represented in a modeled receiver design in the simulation environment.

Using this new technique, RF measurements that aren't typically performed in the digital domain, such as EVM, can now be applied after the analog-to-digital conversion process. This capability should enable RF system engineers to partition and verify RF performance metrics across the analog-to-digital-converter boundary. As the RF and digital domains become more tightly integrated, these combined solutions can be utilized in a vast number of applications. The flexibility that's provided by integrating simulation and test solutions together can help to address emerging design and verification challenges. It also will help to bridge the gap between RF, analog, and digital design teams.

The authors would like to recognize Bert Esser and Guy McBride of Agilent Technologies for their early contributions in the work presented in this article.

TAGS: Digital ICs
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