In high-speed digital signal-processing systems, designers must keep pace with the rising speeds of continuously incoming signals, while simultaneously achieving excellent filter performance in terms of flatness across the bin (data point), and rapid cutoff. Up until now, the choice has been between a programmable DSP approach with a fast fourier transform (FFT) algorithm, and hardware devices (FPGAs or ASICs) with an FFT or pipelined FFT.
A new, special-purpose piece of hardware IP called Pipelined Frequency Transform (PFT) has been developed and patented by the British company RF Engines Ltd. (RFEL). Using the PFT, designers now achieve a totally new quality of real-time data in frequency transformations with significantly less hardware than by using DSPs running FFTs. The PFT acts as a multiple stack of digital frequency converters and provides conversion and filtering of channels across a spectrum bandwidth of up to 100 MHz. This function is carried out in real time at the analog-to-digital-converter (ADC) clock rate with all channels available for onward processing.
By employing a PFT, it's possible to process the information of an ADC running at over a 200-MHz sampling rate, in real time without losing data, while providing multiple individual channel outputs at baseband (complex I and Q channels). The PFT can be considered as the exact equivalent of a massive bank of finite-impulse-response (FIR) filters and frequency converters.
The PFT core is applicable wherever FFTs, digital downconversion, or multiple FIR filters are used, and where a wideband spectrum must be channelized and the cost of individual frequency converters would be prohibitive. Another use is as a replacement for the traditional FFT, where the PFT provides significantly improved frequency "bin" selectivity and flatness, as well as real-time pipelined processing. Where requirements for a large number of channels and good filter performance exist, techniques like the FFT become uneconomical, and the PFT provides the optimum solution.
The PFT can be supplied as firm or hard IP, depending on the application and performance requirements. The PFT core will be parameterized to enable fine-frequency tuning of the hardware design for specific applications. This will let the designer focus the PFT's performance on specific center frequencies and resolution bandwidths defined within the spectrum, and save even further silicon by not processing unwanted channels. Designers will also be able to define the final filter performance for specific applications.
Key areas for the PFT's use include broad-bandwidth applications of up to 100 MHz, such as next-generation mobile phone basestations, spectrum analyzers, radar, and electronic surveillance equipment. All require conversion and filtering of channels (from a few to thousands) in real time, with all channel signals available for onward processing.
The PFT core has proven invaluable in a number of ongoing applications. In one project, there was a need to continuously monitor an entire 80-MHz band with under 100-kHz resolution, an update rate of over 200 kHz, a 75-dB dynamic range, and across-the-bin ripple of under 0.1 dB. All hardware for this was achieved in a PFT-based approach that implemented just one Xilinx XCV3200E Virtex-E 32-Mgate 35- by 35-mm FPGA.
Another project called for the continuous monitoring of an entire 4-MHz bandwidth with under 200-Hz resolution, an update rate of more than 200 Hz, a dynamic range of more than 130 dB, and across-the-bin ripple of less than 0.2 dB. Here, only two Xilinx XCV2000E Virtex-E 2-Mgate FPGAs and eight external RAMs were needed for the hardware using a PFT approach.
The PFT approach radically differs from FFT and pipelined FFT approaches. FFTs are based on multiply-and-accumulate operations (MACs), while PFT uses only fixed shifts, adds, and delays. Because complex multiplication isn't a fundamental part of the basic PFT, this new architecture saves much in the silicon area and in power consumption. As a pipe-lined flow of data from input to output in direct progression, a PFT is additionally well suited for implementation in both FPGAs and ASICs.
The PFT takes information from an ADC with an effective spectrum bandwidth of up to 100 MHz and provides the number of point transforms re-quired by the designer, whether it's 128 or more than 32,000 points. A PFT can provide simultaneous outputs of PFTs with different numbers of bins and resolution bandwidths (RBWs).
With an FFT, it's difficult to realize a flat frequency response across a bin while also maintaining good isolation of adjacent frequency bins. "The PFT's individual bin filter performance far exceeds that available from any other type of process in real time, and as this is a hardware implementation rather than software running on a programmable DSP, we achieve an order of magnitude better performance in high-end applications," says John Lillington, chief executive officer and chief technology officer of RFEL.
"Typical filter stop-band rejection is better than 75 dB with an 8-bit ADC data input," he adds. "There's a tradeoff between dynamic range, selectivity, throughput rate, and silicon gate requirements, which are all under the designer's control. We're currently working on designs with dynamic ranges well in excess of 100 dB."
The PFT function can accept data that has al-ready been downconverted to complex baseband I & Q. If required, the input distributed half-band filter (DHBF) can be provided as part of the RFEL IP.
The basic PFT architecture uses a series of frequency-splitting stages to subdivide the original signal band. The PFT uses a pipelined series architecture, whereby the number of bins grows by a factor of two at each stage (Fig. 1). The first stage splits the band in half; the second stage splits the two bands into four parts, and so on, until the required number of bins is achieved. Decimation at each stage ensures a constant data rate through the pipeline, and, therefore, a continuous data throughput without data loss. A PFT n-point transform requires log2(n) complex downconverter/filter stages (Fig. 2).
Because everything is synchronous, the whole system is locked up to the system clock. Real-world problems, however, limit possible use to, say, only 80 MHz out of a 102.4-MHz signal because it's not feasible to utilize the first and last parts of the signal.
So, a 1024-point transform requires a total of 10 PFT stages, and a 16-kpoint transform needs only 14 stages. By comparison, to provide an equivalent function to the PFT using standard techniques, n-off complex converter/filter modules are necessary. For instance, a 16-kpoint transform would require 16,384 modules. Obviously, this isn't an efficient use of silicon.
The flexibility of the PFT architecture means that by adding silicon, the number of points can be increased for greater resolution. Conversely, finer resolutions can be achieved by using a smaller input bandwidth.
As mentioned earlier, FFT techniques, including Pipelined FFTs, may be used to produce a large number of equally spaced channels quite efficiently. But a problem arises when trying to achieve a large number of channels and good filter performance simultaneously. A standard, unweighted FFT will result in effective filter performance, shown by the yellow curve in Figure 3a. (One example is a simple sinX/X response.) This means that the filter stop-band performance is poor (the first sidelobe is only 13.5 dB down), and that there's roll-off within a bin (bin width being defined as the input sample rate Fs divided by the number of bins).
By comparison, the PFT has a very flat frequency response across a bin and then cuts off very rapidly to the design stop-band level (approximately −85 dB in this example). The degree of flatness and stop-band level are under the designer's control using standard FIR filter design techniques.
The standard approach to improving stop-band performance with an FFT is to employ weighting or "windowing" of the time-domain data. A number of standard windows exist, including Hamming, Hanning, Kaiser, and Blackman-Harris. Figures 3b and 3c clearly show the superior PFT filter performance, even against weighted FFTs. Although longer overlapped FFTs with complex weighting can be employed to improve filter performance, the PFT wins on efficiency, typically using 50% less silicon.
"Compared to an equivalent FFT implemented in a fast programmable DSP, the PFT is up to 20 times faster," says Lillington. For example, with an ADC clock of 204.8 MHz (this number results in integer numbers for the downconverted signal frequencies), a typical FFT speed would be 80 µs for a 1024-point FFT. But a PFT only requires 5.0 µs for the same result. Within 80 µs, the PFT can perform a 16,834-point transform because it's cascadable for higher resolutions. It's a pipelined process, so cascading means putting several elements in series. For instance, if you want eight points, then you need three stages; if you want 16 points, you need four stages, and so on.
"We can typically achieve a stop-band rejection of 75 dB with 8-bit data," explains Lillington. "We're currently working on designs offering stop-band rejections well over 100 dB from a 12-bit ADC input. The frequency response across the bin is flat—around ±0.2 dB."
As Lillington points out, the PFT can be scaled to suit the application, and examples of current projects include eight channels for a communications device and a military application requiring 32k channel analysis.
In addition, the PFT architecture can output PFTs of different bin sizes and RBWs simultaneously, like a 256-point PFT with 400-kHz RBW, and a 16-kpoint PFT with a 6.25-kHz RBW. This can be highly relevant, particularly for military and surveillance applications. Fleeting signals in the wider RBW can be captured and analyzed in more detail in real time, while monitoring of the wider spectrum is maintained.
Pipeline processing implies that there will be no gaps in the data, enabling the tracking of very fast fleeting signals. The waterfall plot in Figure 4 shows a surface plot with 30-µ s pulses switching between four frequencies and a signal sweeping at greater than 80 GHz/s, which can be clearly identified. The implications for electronic warfare and signal-intelligence designs are significant, and on some major programs, the PFT is already being designed in.
Price & Availability
The basic version of the PFT IP is available for implementation into customer hardware (FPGA or ASIC). Evaluation models can be provided in System View, Matlab, or VHDL. A user guide also is provided to aid setup. These evaluation models are intended to allow testing of the PFT's performance. They're available for a small charge that covers dedicated support from RFEL.
Before year's end, a tuneable PFT will be available. RFEL is working on a 14-bit version as well as an inverse PFT (IPFT) that will enable the assembly of numerous individual channels into a specific signal.
Pricing involves four stages: an evaluation license (from a nominal charge up to $40,000), a modification contract (cost is determined by the amount of modification needed in the PFT design), an application license (either a one-time upfront payment, or an upfront payment followed by royalty per unit sale), and a support contract.
RF Engines Ltd., St. Cross Business Park, Newport, Isle of Wight, PO30 5WB, U.K.; +44 1983 550330; fax +44 1983 550340; www.rfel.com.