A new next-generation SoC platform directly supports the company's mission to provide customers with a single SoC development platform where design cycles of six months or less are critical. At the heart of the platform is the newest version of the ARCtangent-A5 user-customizable 32-bit RISC/DSP microprocessor core. The platform also includes the ARChitect processor configuration tool for integrating peripheral IP, such as Hi-Speed USB 2.0 and Ethernet, and a new GUI-enhanced version of the MetaWare SeeCode debugger. The ARCtangent-A5 inherits the feature set of the previous generation A4 processor, but adds new capabilities, including the ARCompact instruction set, more instruction slots for improved extensibility, peripheral support and additional DSP instructions and features. The optimized, mixed 16/32-bit code density ARCompact Instruction Set Architecture reduces code size by more than 30% when compared to the previous generation A4. The ARCtangent-A5 processor also supports the emerging, open-standard BVCI protocol and has optional AMBA bus support. With the GUI-based ARChitect processor configuration software tool, the company says developers can quickly integrate custom extension instructions, condition codes and auxiliary registers as well as its pre-integrated, application-specific peripheral soft IP blocks. The MetaWare SeeCode debugger has the ability to debug single or multiprocessor systems. Enhancements made to the SeeCode GUI include consolidated windows within a single frame and convenient tabs for browsing through tiered windows. For further information and pricing, contact ARC INTERNATIONAL, San Jose, CA. (408) 437-3400.
Company: ARC INTERNATIONAL
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