Electronic Design

Sonet/SDH Clock-And-Data-Recovery IC Sets Small-Size And Low-Power Milestones

Multirate physical-layer device fully complies with Sonet/SDH and Gigabit Ethernet requirements.

The increasing popularity of the Internet has fueled an explosive demand for wide-area networks. To accommodate this expansion, equipment providers must constantly increase the port densities of their machines. This places severe size and performance constraints on the components that are needed to build these machines. One such critical component is the clock-and-data-recovery (CDR) IC.

Well aware of this challenge, Silicon Laboratories Inc. of Austin, Texas, has created a revolutionary CDR device with wide implications for space and power savings. Known as the Si5020 and designed for Sonet and Gigabit Ethernet applications, this chip is part of Silicon Laboratories' SiPHY family of devices.

Claimed to be the smallest CDR IC, the Si5020 has a footprint of only 4 by 4 mm. Packaged in a 20-pin micro-leaded package (MLP), the chip is said to be five times smaller than any currently marketed CDR IC with comparable performance (Fig. 1). This small size also contributes to its typical low power dissipation of 300 mW with a usual supply current of 120 mA, when operating from a single 2.5-V supply. That's 50% less power consumption than similar devices.

But that's not all. This highly integrated device requires no external loop capacitors, as do other devices on the market. This feature is possible thanks to a proprietary DSP-based phase-locked-loop (PLL) circuit that dramatically improves its performance (Fig. 2). The company calls this "DSPLL technology," which greatly simplifies Sonet/SDH jitter compliance in multigigabit fiber-optic communication systems. Such systems include optical transceiver modules, digital cross-connect switches, ATM routers, test equipment, and regenerators.

Meeting Jitter Specifications
The Si5020 meets or exceeds all Sonet/SDH and Gigabit Ethernet jitter specifications. For Sonet/SDH applications, minimum peak-to-peak jitter tolerance ranges from 0.15 to 15 unit intervals (UIs) for the OC-48, OC-12, and OC-3 modes, depending on the test-condition frequency. Maximum jitter-transfer bandwidth for all three modes is 2.0 MHz, 500 kHz, and 130 kHz, respectively.

For Gigabit Ethernet applications, minimum peak-to-peak jitter tolerance per the IEEE 802.3z specification is 600 and 370 ps per clauses 38.68 and 38.69, respectively. Other specifications include 0.1-dB jitter-transfer peaking, a 100-µs acquisition time, and rms jitter generation (with no jitter on the serial data) of 0.01 UI maximum.

The CDR IC's PLL recovers a clock that's synchronous to the input data stream. This clock is used to retime the data. Both the recovered clock and data are output synchronously via current-model logic (CML) drivers. While it's designed to be tolerant of input-signal jitter, the PLL still provides reliable operation with fewer data transitions than either the Sonet/SDH or the Gigabit Ethernet specifications require.

The DSP's algorithm on the chip integrates the phase-detector error term and provides that result to a voltage-controlled oscillator (VCO). By digitally controlling the PLL's loop characteristics, any capacitor value (and thus any loop bandwidth) can be realized without having to use an external capacitor, which would contribute to noise and stability problems.

The chip supports Sonet/SDH rates of 2.48 and 1.244 Gbits/s, as well as 622.08 and 155.52 Mbits/s. It also supports a Gigabit Ethernet rate of 1.25 Gbits/s.

Additionally, the chip supports forward error correction (FEC) in Sonet OC-48 (SDH STM 16) applications for data rates up to 2.7 Gbits/s. In FEC applications, the appropriate reference-clock frequency is determined by dividing the input data rate by 16, 32, or 128. The reference-clock frequency ranges from 19.44 to 166.63 MHz.

Device configuration is simplified because the Si5020 automatically detects the reference-clock frequency. Then, the chip reconfigures itself for operation with one of the three common reference frequencies of 19, 77, and 155 MHz.

Price & Availability
The SiPHY family of CDR ICs includes the Si5020 for multirate applications and the Si5018 for fixed-rate applications. In 1000-unit quantities, the Si5020 sells for $73 and the Si5018 for $59. Volume production quantities are expected in the fourth quarter of this year. Now available are two evaluation boards, the Si5018-EVB and the Si5020-EVB.

Silicon Laboratories Inc., 4635 Boston Ln., Austin, TX 78735; (512) 416-8500; fax (512) 416-9669; www.silabs.com.

TAGS: Digital ICs
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