Electronic Design

Super-Smart Power Technology Scales Down To Nanometer Design Rules

As suppliers adopt 0.35-μm and finer CMOS features, they seek system-level integration with on-chip power MOSFETs.

With the thrust toward system-level integration, smart power devices continue to make progress on all fronts. This advancement has enabled makers of smart power ICs to implement on-chip microprocessors/microcontrollers and digital signal processors (DSPs), along with logic, memory, control/protection, and high-voltage high-power switching circuits. Over more than two decades of evolution, both low-voltage and high-voltage circuits have learned to live side-by-side in harmony, as on-chip integration levels and power capabilities continue to evolve. Smart power devices have been transformed into what some have labeled "super-smart" power ICs, heralding an era of programmability and software-controlled smart power solutions.

Concurrently, developers are exploring integration techniques to include functions that earlier were impractical. For instance, researchers have embarked on projects to implement silicon-controlled rectifiers (SCRs) instead of conventional power MOSFETs or isolated-gate bipolar transistors (IGBTs) on a smart power chip. For that, they're developing isolation technologies that can allow high-voltage power SCRs to function peacefully on the same die that houses low-voltage control and logic circuitry. Likewise, others seek methods to include sensors and microactuators within the realm of smart power technology. Upon integrating these sensors on a single silicon die, developers are investigating methods to implement microelectromechanical systems (MEMS) within the reach of a monolithic smart power process that can realize a true system-on-a-chip (SoC) solution.

Other Avenues Also
Developers have also taken different routes, such as scaling down to deep-submicron CMOS for very high integration densities. Experiments with substrates like silicon carbide (SiC) have shown that submicron CMOS circuits can be built on SiC substrates which are able to accommodate large power structures. Using SiC substrates allows low-voltage control, diagnostic, and protection functions to coexist with high-power devices on the same die.

Speaking of deep-submicron processes, key super-smart power IC suppliers like Motorola Inc. and STMIcroelectronics have begun to migrate toward 0.35-µm and finer CMOS design rules. As these companies scale their respective bipolar-CMOS-DMOS (BCD) processes to finer geometries, they have tackled isolation problems. This has enabled them to bring both low-voltage CMOS and high-power DMOS switching circuits on the same piece of silicon, within close proximity of each other.

Copper Metallization Added
As this technology evolves with scaling, new metallization schemes are being deployed. For example, to cut gate delays and improve electromigration ruggedness, dual-damascene-based copper metal interconnects are replacing traditional aluminum interconnects. In reality, though, both copper and aluminum metal layers are being incorporated in a single super-smart power device, with the top metal layers implemented in copper to handle higher currents for the power structures, and the lower layers implemented in aluminum for the lower-current logic structures.

Attempting to pack more transistors on a single chip, smart power IC developers at Motorola Semiconductor have successfully merged low-voltage microcontroller core, nonvolatile flash, and other memory types with analog and high-voltage power components on the same substrate using a 0.35-µm CMOS logic platform. This isn't a trivial task, considering the thin epitaxial process involved, which is the company's latest SMARTMOS7 process, and its limited thermal budget. According to Motorola, these hurdles were overcome by combining high-energy implantation techniques with clever doping profiles for p and n layers (Fig. 1).

In this scheme, high-energy implants are implemented in the process prior to field oxidation to realize a thick field oxide in the drift region. The advanced implantation method doesn't cause silicon damage as no major thermal steps are needed after the field oxidation flow.

"Energies of the implant chain are carefully chosen to provide adequate junction depth for a high breakdown voltage without adding any manufacturing complexity to the existing implantation process," says Bob Baird, technology manager for Motorola's SMARTMOS Technology Center.

As a result, the developers have been able to integrate a 65-V reduced-surface-field LDMOS power device, with a wide safe-operating area, into a 0.35-µm CMOS logic platform. In fact, experimental work suggests that by further adjusting the doping profiles, the new method can provide breakdown voltages as high as 88 V.

The process also offers very low RDS(on). In essence, it provides an optimum RDS(on) × area, the figure of merit for an LDMOS transistor fabricated in a deep-submicron CMOS process. Tests indicate that the figure of merit obtained for this high-voltage DMOS structure is 0.56 mΩ × cm2. Aside from providing power MOSFETS with a maximum guaranteed voltage rating of 65 V, this technology supplies low- and high-voltage analog MOSFETSs, npn and pnp bipolar transistors, linear capacitors, and a wide array of diffused and polysilicon resistors.

In essence, the SMARTMOS7 process incorporates capabilities needed for a broad range of voltage applications, from portable power management where the maximum voltage is 7 V, to high-voltage automotive applications in which 50-V capability is necessary. These results were presented at last year's International Symposium on Power Semiconductor Devices (ISPSD 2000) in Toulouse, France.

Complex Audio Functions Possible
"This SMARTMOS7 technology has been specifically defined and driven in close collaboration with our power management and audio IC designers worldwide," states Behrooz Abdi, general manager of Motorola's RF/IF division. "It allows us to integrate complex audio-processing functions with power devices on the same substrate to address low system cost, size, and current drain in portable devices," adds Abdi.

"By optimizing the SMARTMOS7 process for 0.35-µm CMOS, the digital capability for the smart power technology has increased dramatically over the earlier-generation 0.5-µm process," notes Hak-Yam Tsoi, director of SMARTMOS device development for Motorola's DigitalDNA Laboratories. "By comparison, the latest SMARTMOS7 process offers seven to 10 times higher digital density over the previous SMARTMOS5 generation."

This has motivated Motorola's designers to bring programmable logic on-board smart power chips, in addition to 8-bit microcontroller cores, memory, and other low-voltage functions. To keep the costs down, Motorola intends to fabricate SMARTMOS7-based smart power chips by using 8-in. wafers. "This will enable us to offer more integration on-chip without increasing the cost," continues Tsoi.

Motorola has developed custom chips for ink-jet printer and automotive applications using the newest process, and the company intends to take it into production this year. While the SMARTMOS7 process is being tailored for applications requiring more intelligence on-chip, Motorola plans to continue using the earlier SMARTMOS5 process for a wide range of applications, ranging from telecom to automotive markets. With that in mind, the company has further revamped the breakdown voltage capability of the SMARTMOS5 process to as high as 120 V. "We are extending SMARTMOS5 for higher-voltage and higher-power applications," asserts Tsoi.

A Demonstration Circuit
To demonstrate this technology and prove it's feasibility for cost-effective integration, designers at Motorola have developed a 90-V dual-channel high-side driver for gasoline direct-injection circuits used in automotive applications. This circuit shows that both 90-V power MOSFETs and 5-V mixed-signal circuits can coexist side-by-side without degrading performance (Fig. 2). Tapping the high-voltage attributes of the SMARTMOS5 process, Motorola's designers also are readying smart-power devices for emerging 42-V automotive systems.

The Motorola roadmap shows that efforts are underway to extend its SMARTMOS technology to 0.25-µm features (see opening illustration). According to Tsoi, it will take about two years before Motorola is ready for production with a 0.25-µm-based SMARTMOS8 process. The company is projecting features to be scaled down to 0.18 µm by 2003.

To further boost current-carrying abilities of the technology, in addition to enhancing the mechanical properties of the metal layers, researchers continue to refine copper interconnect techniques. Plus, developers are considering four metal layers for SMARTMOS8, as opposed to the three presently utilized by SMARTMOS5/7 processes. Furthermore, to enhance the analog performance of smart power devices, Motorola is investigating a novel thinner epitaxial process for the bipolar transistors. This shallow epitaxial process should provide smaller and faster bipolar transistors without compromising the high-voltage capability of the on-chip power structures.

The SMARTMOS8 process is expected to deliver a factor-of-two improvement in digital density over the SMARTMOS7 process, while also furnishing significant improvement in analog performance. Using this technology, Motorola's designers expect to integrate 16-bit microcontroller cores, nonvolatile flash, EEPROM, and other memory types with analog functions, as well as a high-speed controller-area network (CAN) bus on the same smart power chip that houses high-power DMOS transistors.

As a pioneer in this class of integration, Franco-Italian supplier STMicroelectronics Inc. is additionally pushing its BCD technology into the deep-submicron and nano-meter CMOS arena. By employing a clev-er tilt-boron im-plantation method with different doses and implant energies, coupled with interdigitated aluminum/copper metallization schemes, STMicroelectronics' developers have successfully demonstrated 60-V DMOS structures on a silicon substrate that also accommodates low-voltage 0.35-µm CMOS VLSI circuits.

Furthermore, it employs adaptive reduced surface-field techniques to maximize the on-state breakdown voltage with a very thin gate oxide (7 nm). Called BCD6, the process can easily accommodate DMOS power stages with a 0.35-µm CMOS-based microcontroller core, nonvolatile memory, and logic, as well as bipolar control and protection functions on the same super-smart power chip.

Interestingly, STMicroelectronics is the one that first labeled this level of integration as "super-smart" power. Unlike others, the BCD6 process deploys five aluminum/copper metal levels with an interdigitated layout. It uses copper in the fifth metal layer to handle higher currents, as well as to cut the on-resistance of the LDMOS transistors. Also, the researchers have observed that replacing the fifth layer, which is 3-µm thick, with a 5-µm-thick copper layer cuts the metal contribution to the on-resistance of the power LDMOSFET by about 60%. Plus, to improve the LDMOS device's ruggedness and operating speed for high-current operation, STMicroelectronics uses silicide techniques with low sheet resistance.

The BCD6 process can produce monolithic super-smart power chips that can integrate on the same die 40-V/20-V power DMOS transistors, 0.35-µm CMOS 8- and 16-bit MCUs, logic circuits and nonvolatile memory including flash, and bipolar-derived control/protection functions. The company is preparing a high-voltage version of the BCD6 process too.

While STMicroelectronics continues to scale its BCD processes toward the sub-0.2-µm CMOS region, the company is simultaneously developing BCD on silicon-on-insulator (SOI) technology for high-voltage applications like plasma display drivers and off-line fluorescent drivers. The company's latest BCD roadmap, which extends all the way to 2007, shows a variety of BCD flavors under development (Fig. 3). STMicroelectronics has categorized the BCD technology into three broad application sections: high-voltage, high-power, and high-complexity applications.

For very high-voltage needs, the company is readying a BCDSOI process to handle voltages as high as 1200 V by late 2004. For the near future, however, the supplier has prepared a 1.25-µm BCDSOI200 process with 200-V capability, with plans to scale that geometry to 1.0 µm, while the voltage handling will be pushed to 700 V.

700-V Capability On The Way
STMicroelectronics also aims to move a 1.0-µm BCDSOI process with 700-V capability to the production line by 2002. Likewise, for high-power requirements, the company is adding high-voltage power transistors to its mainstream 0.6-µm BCD5 process, which is presently in the production phase.

Additionally, a version of the BCD4 process is being tailored for applications that demand a few amperes of current with voltages between 80 and 90 V. Finally, for complex high-density requirements, the company is migrating toward sub-0.2-µm CMOS for future-generation BCD8 and BCD9 processes.

Surprisingly, STMicroelectronics is moving directly to sub-0.2-µm geometries, and skipping the interim BCD7 process with its 0.25-µm CMOS design features. While the BCD8 process is scheduled for introduction in the 2002 time frame, the BCD9 process is expected to be ready for fabrication sometime in 2004. According to STMicroelectronics, the BCD9 process will offer 0.13-µm CMOS feature sizes.

While the two key players in this fray have set their goals on accomplishing nanometer CMOS features for their respective smart power technologies, other players are presently in the process of scaling to 0.5-µm CMOS. National Semiconductor, for instance, has scaled its 1.5-µm intelligent power technology, ABCD (or analog BCD as the company prefers to call it), to 0.5-µm feature sizes. Using this advanced process, the co-mpany is pres-ently designing numerous smart power ICs.

"This will enable us to deliver high levels of digital and very fast analog functions aimed at power applications without any compromise," speculates Jon Cronk, applications manager for National's power management products. "We can build good power FETs on it, with extremely good digital and bipolar circuitry," he adds. With 25-V capability, the process can address the power-management needs of notebook computers and cellular phones. But it isn't applicable toward National's simple switcher power-supply line, which requires 40-V capability.

Although National continues to exploit its 1.5-µm ABCD process for building high-performance controllers, the company also is infusing more power into this technology. Efforts are underway to boost its vol-tage-handling ability from the present 50 V to 80 V. At the same time, the company is in the pro-cess of shrinking some existing parts by going to a 0.5-µm ABCD process. By shrinking the die size using smaller design features, National intends to deliver chips in microminiature housings like leadless and microSMD packages, hoping to make inroads into the cell-phone display market.

Additionally, the company is pursuing new applications, such as digitally adaptive switching regulators. National is currently in the qualification mode for the 0.5-µm ABCD process, which is now called PVIP, and expects to start sampling silicon using this process by late this year.

The test vehicle for the 0.5-µm PVIP process is a step-up dc-dc voltage regulator, the LM2621. This chip combines a step-up switching regulator, an n-channel power MOSFET, a current limiter, a thermal limiter, and a voltage reference on a single chip. Though the process is now capable of integrating 8-bit microcontroller cores and memory on the same smart power die, no specific plans were detailed at the time that this report was prepared.

Meanwhile, Fairchild Semiconductor is aggressively raising the bar on its 1.2-µm BCD process, which is comparable to the BCD5 process of STMi-croelectronics. Like National, Fairchild is in the scaling mood, hoping to reach 0.5-µm design rules for its BCD process within a year. Aiming to serve the data storage markets with its new process, Fairchild is seeking to achieve 70-V breakdown ratings for its power MOSFETs.

The process doesn't stop here. Like others, Fairchild has crafted a roadmap that points toward 0.35-µm features within three years. For very high-voltage applications, it has in its arsenal a 3.0-µm BCD process that supports 650-V breakdowns.

Several parts based on the process are already in production. A device that exemplifies the technology is the FSDH0165, an off-line switched-mode power-supply (SMPS) IC that combines a voltage-mode PWM controller with a 650-V SenseFET LDMOS transistor on the same substrate (Fig. 4).

Within two years, Fairchild hopes to inject more strength into its high-voltage BCD process, to support 1200-V applications. As it refurbishes the process for higher voltages, the 3.0-µm BCD process will also be shrunk to smaller design rules for more integration, notes Reno Rosetti, director of strategic planning for Fairchild's analog and mixed-signal division. This high-voltage process is tailored for off-line power supplies.

To offer an optimum price point for a given application, Fairchild has adopted a system-partitioning ap-proach, rather than crafting a total SoC solution. "Though the process can pack an SMPS controller, protection circuits, logic, and power MOSFETs on the same monolithic die, we're creating building blocks for smart power solutions," asserts Madhu Rayabhari, director of strategic marketing for Fairchild Semiconductor's analog and mixed-signal division.

Armed with junction-isolated CMOS-DMOS fabrication technology, Supertex Inc. is readying a BCD process that promises to bring programmability to its high-voltage ring-generator chips for tele-communications. As a result, the company will en-able digital programming of amplitude, ringing, and dc offset, thereby providing flexibility to ad-dress global requirements.

To reduce the die size of its high-voltage display driver chips, the company also is exploring other power structures that will improve power device densities substantially. For that task, Supertex is developing a dielectric isolation that will allow its designers to use SCRs instead of conventional power MOSFETs in high-voltage display driver ICs. In fact, under a contract from the United States Display Consortium (USDC), the company is readying high-voltage plasma display drivers with integrated high-speed SCRs and logic functions on the same monolithic die.

Others racing to deliver a complete power supply on-chip include California Micro Devices Corp., Semtech Corp., Philips Semiconductors, and Texas Instruments Inc. For applications that need multiple output voltages, these companies are packing two or more voltage regulators that can be digitally controlled via some sort of logic or microcontroller.

Companies Mentioned In This Report
California Micro Devices Corp.
(408) 263-3214
www.calmicro.com

Fairchild Semiconductor
(888) 522-5372
www.fairchildsemi.com

Motorola SPS
(480) 413-4260
www.motorola.com

National Semiconductor
(408) 721-5000
www.national.com.

Philips Semiconductors
(408) 991-2000
www.semiconductors.
philips.com

Semtech Corp.
(805) 498-2111
www.semtech.com

STMicroelectronics
(781) 861-2650
www.st.com

Supertex Inc.
(408) 744-0100
www.supertex.com

Texas Instruments Inc.
(800) 477-8924, ext. 4500
www.ti.com

TAGS: Digital ICs
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