With 2014’s arrival, I’m pleased to say we all have successfully made another trip around the sun. As the IC industry does every year, we’ve seen material progress in preparing for a number of future technology nodes. It’s a good time to reflect back on some interesting events, as well as look forward into the new year.
The first real 20-nm IC designs went into production in 2013. We saw 20-nm production designs from a handful of the industry-leading companies, with about a dozen different major fabless companies doing production tapeouts or test chips. As is the case at every new node introduction, there were unforeseen IC design, foundry deck/process design kit (PDK), and EDA tool interactions. With the ever-increasing complexity of physical verification node-over-node, partnering with your foundry and key EDA supplier proved essential to quickly characterizing and resolving such problems.
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Three factors were critical to success in 2013: using the same EDA tool suite that your foundry uses internally; three-way non-disclosure agreements (NDAs) to enable open communication; and sharing of design information and other data that manifests the technical issue. Companies that had these three elements in place resolved problems quickly, and their 20-nm tapeouts hit their targeted schedules.
There were some other interesting trends around the more advanced nodes—say, 28 nm and below. We saw some significant increases in engineering R&D staff, primarily designers and software engineers. We also saw major staffing increases at a significant number of the market-leading fabless companies, mostly at offshore locations. This ramp-up is being driven primarily by the need to support increased designer activities, given the added design and verification complexity, double/multi-patterning requirements, and system supplier demands to provide supporting software for ICs.
More than Moore (i.e., 2.5D and 3D ICs) was much quieter in 2013. It feels like we’re in the lull of the adoption cycle just now. For some years, we were in the hype stage and saw a number of interesting early-adopter product releases from companies such as Xilinx. Although we continued to see a handful of interesting design releases, and even more customer evaluations, it seems like companies are still trying to determine which products will benefit the most from pursuing 2.5D and 3D IC configurations. Memory on memory, image sensor on logic, microelectromechanical systems (MEMS) on logic, and memory on SoC/CPU/GPU/FPGA still look like the early contenders.
Next year, the 20-nm node will ramp to a larger production volume. Look for as many as 40 fabless companies doing production design tapeouts or test chips. With 20-nm ICs becoming more common, we can all look forward to faster and more feature-rich servers, PCs, smartphones, and other devices. We also can expect our teenagers to ask for these new products as soon as they roll off the manufacturing line.
In parallel with the production deployment of 20 nm, the foundries, intellectual property (IP) suppliers, and EDA vendors have invested heavily in preparation for 16 nm/14 nm. As a reminder, 16 nm/14 nm are the different marketing names used for the node following 20 nm by the industry’s foundries. Both 16 nm and 14 nm comprise a finFET transistor with a 20-nm back end of line (BEOL) that, like 20 nm, uses double patterning. Over the last year, the major foundry ecosystems largely moved from alpha or beta (v0.x) versions of their design rule decks and PDKs to versions more suitable for production (e.g., v1.x). Fabless customers are just beginning to implement their first test chip tapeouts for 16 nm/14 nm, and 2014 will see most of the 20-nm early-adopter customers also preparing their first 16-nm/14-nm test chips.
Over the last year or so, there has been a lot of discussion across the industry as to whether or not 20 nm will be an abbreviated node, with some expectation that many companies will jump straight from 28 nm to 16 nm. So far, this doesn’t seem to be playing out. Most of the customers moving beyond 28 nm are completing one or more tapeouts at 20 nm before beginning 16 nm/14 nm. Even those customers that we are already working with on 16 nm/14 nm have plans for additional 2014 tapeouts at 20 nm. Why?
Customers that want or need to move beyond 28 nm for competitive reasons can’t wait for 16 nm/14 nm, because their competitors are producing 20-nm designs. Being late to market can be a company killer. Cost is also a factor—20 nm was significantly more expensive than 28 nm for wafers and masks, and with the more complex finFET transistor, 16 nm/14 nm brings even more costs. Although the 16-nm/14-nm node-over-node percentage cost increase over 20 nm is expected to be much smaller than the 20-nm percentage increase over 28 nm, those additional costs are still a material part of the decision to move to the next node.
Meanwhile, IC scaling continues to march on. In parallel with the production ramp at 20 nm, and 16-nm/14-nm test chips, 2014 will see the expansion of work across the ecosystem for 10 nm. Begun in 2012, 10-nm early process development and EDA tool development ramped up in intensity in 2013 and will be full speed ahead in 2014. First alpha/v0.x version decks are already available for the leading EDA tools and are being used for process development and early IP development. 2014 will be spent maturing the process, IP, and EDA solutions.
2014 should be a very interesting year, with a breadth of activity across three technology nodes. 20 nm will move from the early-adopter crowd towards more mainstream production customers, while 16 nm/14 nm will see many test chips in preparation for its production ramp. 10 nm will take its first baby steps. Certainly, 2014 shouldn’t go wanting for something interesting to work on.
Michael White is the product marketing director for Mentor Graphics’ Calibre Physical Verification products. Prior to Mentor Graphics, he held various product marketing, strategic marketing, and program management roles for Applied Materials, Etec Systems, and the Lockheed Skunk Works. He received an MS in engineering management from the University of Southern California, and a BS in system engineering from Harvey Mudd College.