Full-Circuit PLL Verification

Sponsored by: Mentor Graphics

When designing PLLs in nanometer CMOS, it is essential to validate the closed-loop PLL performance metrics with nanometer SPICE accuracy before going to silicon. Transistor-level, closed-loop PLL verification has been impractical due to traditional SPICE and RF simulator performance and capacity limitations. By using Analog FastSPICE, designers do not have to trade accuracy for performance.

Mentor Graphics

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