Electronic Design
Node Wars: A Look Back at 2014, and Different Roads for 2015

Node Wars: A Look Back at 2014, and Different Roads for 2015

Michael White, Director of Product Marketing, Mentor Graphics

It’s a fun time of year to take stock of all that the industry achieved in the past year, and to anticipate the interesting trends coming in 2015.

2014—The Year 20 nm Hit It Big

As I discussed in this column a year ago, some initial 20-nm integrated-circuit (IC) designs went into production in 2013, but big growth wasn’t expected until 2014. That growth has certainly come to pass, with a big jump in foundry revenue at 20 nm in the second half of 2014. For the foundry leaders, 20 nm is now a solid ~10% of their total revenue, which represents a 10X increase year-over-year (YoY) in revenue. Not bad, eh? Why such a proliferation of 20-nm designs, you might ask? The simple answer is the plethora of advanced mobile devices we can’t live without these days—the iPhone 6/6+ being the most visible example. A number of 20-nm chips reside in the iPhone 6/6+, and sales have been brisk.

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Expect to see more 20-nm designs over the next year or so as companies implement incremental improvements and respins of successful products, as well as make the decision to stay at 20 nm or move on to 16/14 nm. The 16-/14-nm node offers some attractive benefits, such as lower power, but also brings more design complexity, using FinFETs rather than the bulk CMOS dominating 20-nm designs. In addition, a node-over-node increase in wafer cost must be incorporated as part of the business plan for a design start at 16/14 nm. The wafer cost percentage increase of 20 nm to 16/14 nm is reported to be less than that of 28 nm to 20 nm, but it is still material.

Last year was also the year of 16-/14-nm test chips. Many of the leading fabless companies released one or more test chips this year. Half of the IC Insight’s Top 20 will have completed a 16-/14-nm tapeout by the end of 2014. 

2015 and the Era of Many Options—Advanced Nodes

This year will see a growing number of 16-/14-nm test chip tapeouts, as well as early production designs. Industry leaders are talking on the order of 50 tapeouts between now and the end of CY15. Fabless companies that have already completed their initial test chips for 16/14 nm are now talking about their first production designs.

In 2015, we’ll also see intense work on 10 nm. Foundry-certified sign-off Calibre decks are already available for the leading foundries, enabling their key intellectual-property (IP) and fabless partners to start initial IP development. Meanwhile, the foundries will continue to implement process and design-rule refinements to prepare for the first test chips in the second half of CY16 or early CY17.

2015 and the Era of Many Options—“Advanced Mature” Nodes

So much of the industry discussion revolves around bleeding-edge nodes, but some very interesting and important changes are happening at 28 nm up through 0.18 µm. Advanced economies worldwide (e.g., Europe, Japan, China, U.S., etc.) have an ever-growing demand for smarter, lower power, more interconnected, and data-rich computing—a.k.a. the Internet of Things (IoT). Consumer demand for these capabilities is driving some interesting trends in the lifespan of the 28-nm through 0.18-µm nodes.

In a nutshell, those nodes that best support radio-frequency (RF) and mixed-signal IC designs with low power, low cost, and high reliability are enjoying a much longer life than would typically be expected. Why, you might ask again? The iPhone, GoPro camera, Nest thermostats, etc., may all have advanced-node application processors and memory (e.g., 20 nm, 28 nm, and so on), but the smart-power, Wi-Fi, Bluetooth, etc. features that provide longer battery life and desired connectivity are far better delivered from a cost/performance standpoint via 45-/40-nm, 65-nm, 130-nm or 0.18-µm processes.

Another interesting impact of these “advanced mature” nodes (i.e., extension of mature nodes to new applications) concerns changes being driven in the design rules and associated manufacturing processes. For example, when the 65-nm node was first created, it was obviously the most advanced process at that time. As is typical, a new technology node (like 65 nm back in the 1990s) is first developed for bulk CMOS logic. The process/design rules then become optimized for this application. Roll forward to 2015, and this same process line is being “retooled” to produce an assortment of mixed-signal IC designs (e.g., Wi-Fi, Bluetooth, etc.) with design rules and a process that never envisioned such products or their increased design complexity.

With the growing interest in delivering products to IoT applications, and an overall trend of being “green,” there’s also a huge push for lower power devices. The net impact of these trends includes changes to, or additions of, design rules and yield detractor patterns/rules, as well as many new device types being added to the decks used in physical-verification tapeout. Why is this important? Well, because it means the notion that mature nodes are static, and thus any physical-verification deck and EDA tool can be used, just isn’t true.

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Time-to-market for an advanced Wi-Fi, Bluetooth, etc. chip built on an “advanced mature” node is just as important as a 16-/14-nm application processor for a next-generation smartphone, which means the same physical-verification recommendations hold for both. Because the process and design rules are continuously evolving in both, use the sign-off tool favored by your foundry, and you’re good. Use a “follower” EDA tool, and you risk missed errors and a longer time-to-market.

Summary

2015 should be a very interesting year, regardless of what technology node you’re targeting with your products. We will see continued growth in the number of 20-nm designs, and 16/14 nm will see a transition from test chips toward production designs by the end of the year. Early adopters at 10 nm are already starting to create IP. For those pursuing IoT and connectivity-related applications, you will see continued evolution of 0.18-µm, 130-nm, 65-nm, 45-/40-nm, and 28-nm processes, rule decks, and design rules to support the more complex and ultra-low power designs demanded by the market. Plenty of very interesting challenges to work on. It should be fun!

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