Today, almost every embedded system contains three key building blocks—a processor, some memory, and some logic. Traditionally, field-programmable gate arrays (FPGAs) have been restricted to the latter because implementing the processor portion of the design in the FPGA logic was very inefficient. Often, it also yielded relatively low performance.
To solve the performance issue and deliver a single-chip solution, designers at Altera developed a dual implementation approach. In one direction, designers at the company have crafted their own RISC processor, which employs a 16-bit instruction set and can be compiled with a 16- or 32-bit-wide datapath. The Nios processor is designed as a "soft" core. That allows it to be deployed using the programmable logic and embedded memory of the FPGA.
The second path taken by Altera leverages partnerships with Advanced RISC Machines Ltd. (ARM), Cambridge, U.K., (www.arm.com) and MIPS Inc., Mountain View, Calif., (www.mips.com). This provided the company with licenses for the 32-bit ARM9 Thumb and the MIPS32 4K processor cores, plus the peripheral cores needed to create a complete high-performance system solution. Implemented as "hard" cores, these processor blocks can be dropped into the base silicon of the FPGA, replacing a block of gates and delivering top-notch performance. Altera also is holding discussions with Motorola Inc., Austin, Texas, (www.motorola.com) to obtain a license for the 32-bit PowerPC architecture and various core derivatives.
Both the soft and hard approaches are part of what the company calls the Excalibur embedded processor solutions. The embedded processors can be combined with the APEX FPGA family to create programmable system-on-a-chip solutions. These grant system designers ultimate fast-turnaround and flexible solutions. The APEX family provides designers with a series of FPGAs ranging in capacity from 60,000 to over 1.5 million gates, and an abundant amount of on-chip static RAM. Additional resources on the FGPA family chips include content-addressable memory structures and true low-voltage differential signalling (LVDS) I/O cells. These can reach data rates of 840 Mbits/s.
The Nios processor soft core provides a 50-MIPS-throughput processor. This is good for system designers who don't feel they have the volume to justify the cost of a customized FPGA chip with a hard core. The core includes a five-stage instruction pipeline and can execute an average of one instruction per clock cycle. Using the Nios core with a 16-bit datapath requires about 1000 logic cells on an APEX EP20K200E FPGA, or about 12% of the gates (Fig. 1). The 32-bit version requires a few percent more. Altera also plans to offer the Nios core on its APEX FPGA family to address more cost-sensitive applications.
The performance of the Nios core allows it to handle many embedded control applications. The scalable datapath suits it for applications that require either 16- or 32-bit computations, while the 16-bit instruction set allows for very high code densities. The short instruction words will minimize the amount of off-chip Flash or ROM necessary for program storage.
On the company's larger APEX EP20K1500E, the processor consumes just 2% of the chip's resources, leaving most of the on-chip logic and memory available for customized peripherals and specialized logic functions. The small size of the Nios core also allows designers to use multiple instantiations of the core on a single FPGA. Alternatively, multiple cores can work in an array like that employed in network processors (Fig. 2).
Targeted for compiled embedded applications, the Nios processor instruction set packs instructions especially helpful in embedded applications. An example is the single-instruction bit-test-and-skip. The core is supported by the GNUPro embedded system development tools which were created by Cygnus, a division of Red Hat Software Inc., Research Triangle Park, N.C., (www.redhat.com). A debugger that's part of the tool set communicates with the processor logic over Altera's MasterBlaster or ByteBlaster programming cables. Additional future partnerships will extend the software capabilities to include such real-time operating systems as eCos, Linus, and pSOS.
Included in the support is a development kit with all the necessary peripheral cores. These comprise a UART, a parallel I/O port, counter/timers, and interfaces for external SRAM and flash memories. Also in the kit are a C/C++ compiler and a source-level debugger.
Additional peripheral support functions will be released later this year, extending into next year. Furthermore, any of the intellectual property blocks available for the APEX family can be co-integrated on the FPGA too.
Also included is the Altera Quartus development software for configuring the FPGA, as well as verification tools and a hardware development board that contains an APEX EP20K200E FPGA. By using the MegaWizard interface in the Quartus design tools, users can map a system and configure the memory and peripherals on the FPGA. The Nios core can be extended by adding conventional memory-mapped peripherals on the chip (using the FPGA logic), mapping readable/writeable devices into the processor's register file, and incorporating user-designed function blocks directly into the processor's ALU.
When higher-throughput processors are needed, designers can opt to use an APEX family FPGA with either the MIPS or ARM processor cores and support functions preintegrated on the silicon (Fig. 3). Because the cores are predesigned and they're integrated in the base silicon, they keep the required chip area to a minimum, but they can include large register banks or a reasonable cache memory. They can deliver throughputs of 100 to 200 MIPS. Development kits for the ARM- and MIPS-based APEX FPGAs will be available late this year. Software development tools already available for the ARM and MIPS processors can be used to develop and debug the application software.
Price & Availability:
The Nios core is available immediately. When used in high volume, it can be licensed for about $5 per instance. Licensing fees for the other processors are negotiated on an application-by-application basis. The Nios development kit sells for $995.
Altera Corp., 101 Innovation Dr., San Jose, CA 95134; Contact Cliff Tong at (408) 544-7000; www.altera.com/cuttingedge.