The ARM architecture covers a range of 32-bit processor cores. It can be combined with the ARM Jazelle Java accelerator or third-party Java coprocessors to pump up Java application execution speeds. ARM's low-power operation and Java support has made it a popular choice for portable devices.
To minimize power consumption, the architecture can be stripped. The architecture supports its standard 32-bit instruction set, which can coexist with the 16-bit Thumb instruction set. Thumb instructions are translated to 32-bit instructions, slowing execution a little. But code size is significantly reduced, which allows 32-bit cores to compete with 8- and 16-bit microcontrollers. An operating system can run a mix of 16- and 32-bit applications.
ARM's AMBA specification provides a standard interface for third-party IP to interface with the processor core. AMBA defines the multimaster advanced high-performance bus (AHB) and the advanced peripheral bus (APB). The latter provides a low-gate-count interface for general-purpose peripherals like timers, UARTs, and parallel ports.
Advanced debugging support can be included using the embedded trace macrocell. It supports instruction and data traces, compresses trace data, and includes complex trigger mechanisms. www.arm.com
The PowerPC architecture spans 64- and 32-bit processors, but the former are standalone processors for servers and workstations. The 32-bit cores are found in embedded applications, including custom SoC designs and off-the-shelf SoC chips. The embedded PowerPC is popular in communications and automotive environments.
A wide range of core designs make use of the PowerPC architecture. The PowerQUICC cores are designed for communication environments. IBM's PowerPC 440 uses the 128-bit CoreConnect bus interface. CoreConnect provides high-speed, multiprocessor support in addition to on-chip peripheral-bus support.
The PowerPC architecture is finding its way into myriad applications because of various enhancements, such as symmetric multiprocessing (SMP) support. The AltiVec SIMD support processes 128-bit data in scientific, 3D, and multimedia applications. Motorola's PowerPC processors will also be among the first to incorporate RapidIO host interfaces as part of the core. RapidIO provides an efficient packet-oriented interface between processors and devices. www.motorola.com, www.ibm.com
The MIPS architecture delivers 32- and 64-bit processing, depending on the core chosen. The 64-bit architecture is a superset of the 32-bit architecture. Originally targeted at workstations and servers, MIPS processor cores are almost exclusively found in embedded applications.
The architecture supports application-specific extensions, user-defined instructions, and custom coprocessors. Most developers need these enhancements to tightly integrate surrounding services with the processor core.
Several MIPS architecture enhancements facilitate support for various applications. General-purpose register shadow sets provide improved interrupt performance. Enhanced bit-field manipulations improve performance when manipulating high-speed data streams carrying protocols such as transmission control protocol (TCP)/Intellectual Property (IP). The MMU architecture now supports 1-kbyte pages, which is useful in memory-constrained applications.
Through third-party IP, MIPS supports hardware Java. A number of different Java coprocessors and architectures are available for MIPS cores.
The architecture pushes the envelope in many different areas. Single-instruction multiple-data (SIMD) instructions and registers significantly boost performance for various multimedia and DSP applications. www.mips.com