Surface-Micromachined CMOS Process Enhances IC Tire-Pressure Sensor

Aug. 19, 2002
An innovative design by Motorola's Sensor Products Division in Tempe, Ariz., optimally integrates a surface-micromachined capacitive automotive tire-pressure sensor with a 0.8-µm CMOS double-metal, double-polysilicon process. Improving pressure...

An innovative design by Motorola's Sensor Products Division in Tempe, Ariz., optimally integrates a surface-micromachined capacitive automotive tire-pressure sensor with a 0.8-µm CMOS double-metal, double-polysilicon process. Improving pressure linearity over conventional CMOS designs, this chip includes an optimum signal-processing algorithm and EEPROM to store pressure and temperature calibration data.

A careful examination of conventional CMOS designs showed that designers have to micromachine the sensor element before they perform CMOS' temperature-sensitive steps to maximize sensor performance. The source/drain implants were identified as the temperature-sensitive steps.

The chip has a full-scale output of 0 to 255 counts with a pressure linearity of −1.5% of full scale. The offset temperature coefficient and sensitivity are 0.01 counts/°C and −0.005%/full scale/°C, respectively. Its pressure range is 0 to 637.5 kPa, and its thermal hysteresis is just 0.04%/full scale.

"With most designs, adding a MEMS device to a CMOS process affects performance, either thermally or topographically, and the CMOS Spice design parameters involved," explains Bishnu Gogoi, principal staff scientist for technology development. "We also designed this chip so that we can reuse the CMOS process fabrication steps as much as possible."

In the new process, the pressure sensor's bottom is defined using floating-gate polysilicon, followed by an isolation nitride layer. Next, the spacer layer is defined. The pressure-sensitive diaphragm is then formed using a polysilicon layer. A hydrogen-fluoride solution is used to remove the spacer layer. The etch holes are scaled to complete the formation of the sensor. The CMOS process is resumed with interlayer dielectric layers and metal deposited. Finally, the chip is passivated with the sensor and bonding pads left exposed (see the figure). Although he refused to be more specific, Gogoi says the chip is in engineering evaluation by a number of customers.

For details, contact Gogoi at (480) 413-8836 or [email protected].

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