System in package (SiP) is an invaluable tool for delivering compact silicon solutions. It allows different technologies to combine into a single package, reducing the bill of materials (BOM) of a system while increasing the reliability. It can also lower system design costs since more complex components are combined within a SiP.
There are many SiP implementations, so it’s not surprising that a few myths about this technology may be floating around.
1. There’s no industry agreement on the definition of system in package.
The definition of SiP varies so widely that the first chapter of TechSearch International’s recent SiP report1 includes a list of over 20 definitions, contributed by a range of SiP suppliers and users. To establish the basis for the report and forecasts, the chapter provides the following definition:
“System-in-Package is a functional system or subsystem assembled into a standard footprint package such as LGA, FBGA, QFN, or FO-WLP. It contains two or more dissimilar die, typically combined with other components such as passives, filters, MEMS, sensors, and/or antennas. The components are mounted together on a substrate to create a customized, highly integrated product for a given application. SiPs may utilize a combination of advanced packaging including bare die (wire bond or flip chip), wafer-level packages, pre-packaged ICs such as CSPs, stacked packages, stacked die, or any combination of these.”
By this definition, multichip packages (MCP) and multichip modules (MCM) aren’t considered a SiP, although various suppliers would disagree—this increases the challenge of analyzing and forecasting the SiP market. Many MCPs are combinations of devices that are like stacked-die chip-scale packages (CSPs), where flash and RAM are combined in a die stack supplied in high volumes. MCPs are also similar to MCM or modules, where the solution is a custom assembly format that’s not a standard package platform, like a fine-pitch ball grid array (FBGA).
2. SiP competes with system on a chip (SoC).
They are more complementary than competitive. SoC has long been an effective strategy to integrate established IP blocks for high-volume applications that can absorb the significant complementary metal-oxide-semiconductor (CMOS) design and mask costs (which can exceed $300M) associated with a SoC.2