Triple-level-cell (TLC) NAND is the mainstay for high-capacity flash storage. Storing three bits per cell boosts the amount of information that can be handled by a single chip. However, there are tradeoffs: A cell can handle only so many writes, and packing more data into a cell—and chip—increases the number of errors. Forward-error-correcting (FEC) technology, though, along with other flash-management support, helps improve system reliability.
TLC NAND systems are already taking advantage of 64-layer 3D technology. This is how vendors are able to deliver multi-terabyte solid-state drives (SSD) and terabyte M.2 modules.
The technology continues to advance, as one of the hot topics at the Flash Memory Summit will be 4-bit QLC NAND flash. QLC flash works with existing 3D technology, essentially doubling the available storage.
Western Digital’s 3D QLC flash-memory chips double storage capacity.
Western Digital and Toshiba have already announced their QLC BiCS flash-memory chips (see figure). The 768-Gbit (96-Gbyte) die capacity improves on the 512-Gbit TLC chips. A 16-die stack of the TLC chips provide 1 Tbyte of storage.
The 1-bit, single-level-cell (SLC) and 2-bit multilevel cell (MLC) still have their place, especially in embedded applications. And TLC will not go away. The fact is that it will take time for QLC to become the dominant technology for high-capacity drives. Developers and enterprise manager will still need to consider the cost/performance equation for their storage devices.
If you’re considering QLC NAND, there’s another benefit that awaits: The higher-capacity drives will make it easier to provide configurable over-provisioning that’s already available on high-capacity SSDs like Micron’s FlexPro drives.
