Electronic Design

ARMv7 Makes A Move To Multicore

With its multicore/multiprocessor support, ARMv7 can now handle cache coherency.

ARM's new symmetric multiprocessing (SMP) multicore architecture has found a home in the popular ARMv7 architecture. SMP is similar to the architecture found with ARM's higher-end cores.

However, the new architecture handles up to four cores plus support for accelerator and DMA units (see the figure). The enhancements apply to the low end of the newer Cortex architecture as well. Such an approach provides significantly higher performance than the software-based synchronization used in many custom ARMv7 multicore chips. Such synchronization typically uses a software cache coherent approach that adds significant overhead as the number of processors increases.

FOUR CHANGES
The main ARMv7MP processor core remains the same as the typical ARMv7 core, with four major architectural changes: cache coherence support, L1 cache coherence for system accelerators, TrustZone and Generic Interrupt Controller (GIC) Architecture support, and support for paravirtualization managers.

The instruction and data L1 caches associated with each processing core incorporate cache-coherency support that's synchronized via the snoop control unit (SCU). The SCU also is linked to any on-chip DMA or accelerators. A local coherence bus links these to the SCU. In addition, each master device can lock down blocks of memory in the L2 cache. This can prevent high-bandwidth masters from flooding the cache.

ARM VIRTUALIZATION
One of the other features included with the new architecture is better support for paravirtualization (see "Virtual Embedding" at www.electronicdesign.com, ED Online 10765). Paravirtualization requires a customized kernel of any virtualized operating system. But there are benefits, such as improved system performance.

Higher-end systems often feature more extensive virtual-machine support, which lets a virtual-machine manager (VMM) host unmodified operating systems (see "Platforms Strive For Virtual Security," ED Online 10813). However, this usually is of little consequence for embedded developers who typically have access to operating-system and application code. Paravirtualization is likely to be more important to embedded developers for security, system partitioning, and legacy support.

TrustZone is ARM's mechanism to separate secured and non-secured domains. The GIC is part of the puzzle, since it's possible to route interrupts to the appropriate domain in a multicore VMM environment. Secure cache state is maintained between domains during virtualization traps and request forwarding. This enables the secure management of system resources among cores and security domains.

Processors with this new multicore architecture won't be immediately available. ARM sells cores, not chips. Many of the initial products will be custom and hidden from most developers. Look for this technology to move into standard parts, though, especially the Cortex line.

ARM
www.arm.com

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