Electronic Design

Back To The Future With The 68K

The venerable Motorola 68000 architecture takes a leap ahead with a unique real-time microcontroller architecture from Innovasic Semiconductor.

Looking for a deterministic microcontroller that can be a good target for legacy applications? Then check out Innovasic Semiconductor's fido1100 microcontroller family.

These devices are based on the 32-bit Motorola (now Freescale) 68000 and run an enhanced CPU32 instruction set that was used in the 683xx product line. But the fido1100 is more than just a reincarnation of the CPU32. In fact, just about the only thing the fido1100 shares with the 68K is the instruction set.

Innovasic Semiconductor is known for extended-life replacement ICs, including microcontrollers. The company also customizes new designs for customers. The fido1100 is a little different, though. It targets general developers and combines the ideas and requests of many customers and Innovasic designers.

The starting point is the CISC CPU32 instruction set architecture (ISA), which remains very popular given the success of Freescale's ColdFire product line. The advantage is a plethora of well-tested compilers and tools for the CPU32. The CISC architecture handles non-aligned memory accesses, and Innovasic's version handles endian conversion transparently.

Additionally, many developers are familiar with the 68K architecture that was the basis for the original Apple Macintosh prior to the migration to the PowerPC and now to the Intel Core 2 Duo platform. The Mac may need a heftier processor, but most embedded applications need determinism, not just pure speed.

Innovasic designers built five register contexts around the processor core. One context has supervisor capabilities so the other contexts can be controlled and protected. The memory management unit provides access restrictions to 16 blocks, not virtual memory support. The chip has a 32-bit flat memory architecture.

Each context has its own access restrictions controlled by the supervisor to prevent one application from stepping on another. Also, each context has its own priority, with the system running the highest ready priority context. Contexts can be configured to share the processor resources as well.

Furthermore, contexts can wait on events and communicate with each other, though only one is active at any time. Each context has its own hardware mutex. Software interrupts can be used to coordinate communication between contexts. The hardware has support priority inversion.

Each context also has its own timer and timer interrupt. The processor portion of the chip goes into sleep mode if all contexts become idle waiting for events.

The chip has two memory banks for code and data. The code bank is called Rapid Execution Memory (REM), or sometimes, a deterministic cache. It's essentially fast code memory divided into 2-kbyte blocks that are explicitly loaded in a fashion similar to a cache. It permits high-speed execution of key functions or interrupt routines. Other code will be stored in slower off-chip SDRAM or flash memory.

The approach is a good compromise and very effective in an embedded environment where application code location can be tuned. The 16 REM blocks can be utilized by contexts as needed under supervisor control. This flexible approach is used in peripheral support.

The secret to the fido1100's interface flexibility is the Universal IO Controller (UIC). There are four independent UICs in the chip (see the figure). The UICs are programmable processors, but currently they're designed to run packaged applications to implement a standard set of peripherals.

These peripherals include 10/100 Ethernet, CAN, UART, SPI, I2C, and GPIO (general-purpose input/output). Ethernet still requires an off-chip physical layer (PHY), but it handles everything else in hardware. Ethernet, CAN, and I2C peripherals handle packet addressing.

The UIC will be very useful in the future, enabling developers to customize these interfaces. Many proprietary legacy interfaces are just variations on a theme, and the UIC approach allows customization on-chip.

Other standard peripherals include a dual-channel DMA and an eight-channel, 10-bit analog-to-digital controller (ADC). It isn't the fastest or most accurate ADC available, but it's more than adequate for a wide variety of embedded applications. Other analog peripherals will have to be added as necessary.

Innovasic Semiconductor delivers CodeSourcery's C/C++ GNU toolchain with its development kit. The open-source system includes the graphical Eclipse integrated development environment (IDE).

The debugger is customized to take advantage of the JTAG-based SPIDER (Software Profiling and Integrated Debug EnviRonment) hardware. SPIDER memory or ship it out via a UIC Ethernet port.

SPIDER has conditional hardware breakpoints that can be chained together. It can be used to provide statistical software profiling to identify critical pieces of code that should run in REM. Debug features are context aware, so it's possible to break on code run by a specific context.

One of the major debug features of the fido1100 is the ability to single-step one context while the others continue running. This is very handy in a realtime environment where stopping the entire system can cause major problems. The approach can be used to single-step interrupts as well.

A version of Linux that will be available takes advantage of the context support provided by the fido1100. It also exposes the REM and UIC support as well, allowing the sophisticated applications to be built on Linux instead of building from basic drivers.

Pricing for the fido1100 line will be in the $10 to $15 range. It's available in 208-pin plastic quad flat (PQF) and fine-pitch ball-grid array (FBGA) packages. A development kit also is available.

An interesting side note is Innovasic Semiconductor's normal obsolescence work. The company knows how to preserve its customers' work by delivering long-term solutions for discontinued products, so the fido1100 should be around for quite a while.

Innovasic Semiconductor

fido1100 Specifications

Core: CPU32 code compatible with five contexts
Clock: 66 MHz
Features: zero-overhead Endian conversion, automatic sleep mode when contexts are inactive, non-aligned memory access, memory protection unit
Peripherals: four programmable Universal IO Controllers (UICs); 10-bit, eight-channel ADC; five counter/timers; watchdog and context timers; two DMA
UIC interfaces: 10/100 Ethernet, CAN, UART, SPI, I2C, GPIO
Debug: Software Profiling and Integrated Debug EnviRonment (SPIDER), JTAG Interface: 3.3 V with 5-V tolerant I/Os
Packaging: 208-pin PQFP and FBGA
Pricing: $10 to $15

TAGS: Freescale
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