Electronic Design

Bridge PCI-X To PCI, And PCI-X To PCI-X

The question is simple. Will PCI-X, the Special Interest Group (SIG) extension to PCI, become a mainstream standard? Increasingly, the answer seems to be yes. The tide is shifting toward PCI-X as PCI's successor. Driving this shift to the more-efficient PCI-X bus is emerging PCI-X-compatible silicon. Tundra Semiconductor supplies a critical silicon element—a universal chip that bridges PCI-X to PCI, as well as PCI-X to PCI-X.

The Tundra Tsi320 bridges PCI and PCI-X buses. Even better, it supports so-called non-PC or embedded implementations that require nontransparent bridging between the host system and the PCI/PCI-X subsystems. A nontransparent bridge to a processor subsystem lets that subsystem look just like a virtual peripheral.

So, the subsystem peripheral can control its own memory space and do its own enumeration on power-up. This bridging duality lets engineers use the same chip for transparent (standard PCI host) and nontransparent (embedded) implementations, cutting down on part proliferation.

The bridge chip supports 32/64-bit PCI and PCI-X buses. It handles bus speeds up to 66 MHz for PCI and up to 100 MHz for PCI-X. Current modeling and testing of PCI-X shows that it can drive up to eight 66-MHz slots and up to two 100-MHz slots. The chip, then, can handle a full eight-slot PCI-X segment for CompactPCI-like implementations.

To some, PCI-X is PCI as it should have been done. PCI-X is a subset and superset of PCI. Basically, it builds on PCI, incorporating almost all PCI operations. As a superset, it extends PCI operationally, adding a 64-bit status word sent on the second clock of a transaction.

This status word expands the functionality of the bus. It supports split transactions, separating request from action, and byte-count transactions, running a transaction by counting down the byte count for it. The two main advantages of PCI-X are that its split-transactions convert PCI's slow Reads to fast (separated) Writes, and that it defines a registered interface (all signals are clocked into registers) to more slots at higher speeds.

For a PCI-X interface, the chip supports eight posted writes, 12 concurrent Split-Reads, four Split-Writes, and four concurrent DMA transactions. For PCI, it supports up to eight posted Writes, four concurrent delayed Reads, four delayed Writes, and four concurrent DMA transactions.

Peripherals include a hot-swap-friendly controller, an I2C serial port, dual UARTs, a JTAG port, and a secondary bus arbiter for up to seven external bus masters. It comes in a 352-BGA package and costs $49.57 each in lots of 10,000 units.

Tundra Semiconductor, 603 March Rd., Kanata, ON, Canada K2K2M5; (613) 592-0714; www.tundra.com.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish