Carbon Design Systems has rolled-out its ‘breakthrough’ SOC-VSP product line. It complements the ARM RealView SoC Designer solution by importing Verilog and/or VHDL (RTL) into a RealView SoC development environment. This combination allows a hardware-accurate SoC model with RTL to be profiled, optimised, debugged and validated including the software and hardware content.
System architects, software developers and hardware designers can validate design assumptions and implementation throughout the design cycle. In particular, system architects can profile a SoC with cycle-count accuracy and certified models to find software bottlenecks and establish optimal hardware configurations.
Software developers can get speed debugging firmware on a hardware-accurate model, instead of waiting months for silicon or a behavioural model to be developed. Hardware designers can leverage mixed-level simulation, an integrated debugger, and a plug-and-play interface to an AMBA AHB interconnect, AMBA APB interconnect, or AMBA 3 AXI interconnect.
According to Carbon, this is the first all-software, all-inclusive product of its kind to enable Continuous Validation of software and hardware from concept to volume production.
All standard debugging features are supported: single-stepping of source code; setting breakpoints; tracing registers; memories; and signals–with ‘Carbonised’ RTL hardware models. RealView SoC Designer’s waveform viewer is transaction-aware and animates both transactions and signals. Verilog and VHDL models can be interrogated as standard components. SOC-VSP supports 100% visibility for all RTL signals, registers and memories.