Electronic Design

Chip Set For Symmetric DSL Doubles Twisted Pair's Reach

The two-chip set uses advanced algorithms and an embedded MIPS processor to realize DSL's true broadband potential.

Despite the many exciting advances taking place in fixed wireless, satellite, and optical communications, the task of bringing broadband services that last mile, to the consumer, still falls on the shoulders of plain old copper lines. This copper can take the form of either coaxial cable lines, or the well-established twisted-pair lines that are taking advantage of advances in digital subscriber-line (DSL) technology

Often maligned for its limited reach, and for the need for two twisted-pair lines for high-bit-rate (HDSL) implementations, DSL has had trouble penetrating the mass market. Now Excess Bandwidth, a young startup based in Cupertino, Calif., may have found the path to DSL ubiquity, using advanced, proprietary, training algorithms for training, equalization, and echo cancellation. With support from a high-end, embedded, R4000 MIPS execution processor, the company's engineers have realized a low-cost, low-power, two-chip HDSL2/G.shdsl solution (see "Why HDSL2? It Goes The Extra Mile(s)," p. 72).

The solution comprises two chips—the EBS710-H tunable analog front end (AFE), and the EBS720 digital processing chip. Together, the chips exceed the ANSI HDSL2 specification for 1% worst-case crosstalk and bridge-tap scenarios. Thereby they double HDSL2's specified reach to 1.5 Mbits/s over 18,000 ft. of 26 AWG twisted-pair, or 24,000 ft. of 24 AWG lines. The 1.544 Mbits/s over 9000 ft., that the HDSL2 spec defines, covers up to 50% of all loops, and over 75% of business loops. The symmetrical nature of the specification allows the chip set to readily support the simultaneous data, multiple-voice, and video-conferencing technologies presently appearing.

Taking advantage of the ubiquity of the plain old telephone system's (POTS) twisted-pair infrastructure, DSL, in its various forms, has proven very successful in the face of other copper-based technologies, such as cable. Still, the ever-present demand for more bandwidth, increased services, and greater reliability, combined with the need to extend the range of DSL, has put the onus upon manufacturers to reevaluate the longevity of asymmetric DSL (ADSL). Though it's the most popular version of DSL, advanced alternatives like HDSL stand poised on the sidelines to enter the fray and pick up where ADSL leaves off.

Defined under ANSI standard T1E1.4, the latest incarnation of HDSL, called HDSL2, offers increased reach, extreme robustness and reliability, and fast, symmetrical connections that more readily support the simultaneous data, multiple-voice, and video-conferencing applications coming our way. In addition, the ITU is working on a global, more generic form of HDSL2, called G.shdsl.

While it sounds good in theory, the practicalities of implementing the HDSL2 standard have proven difficult. An extremely high noise margin has delayed the deployment of the technology as semiconductor manufacturers have struggled with issues surrounding equalization, echo cancellation, integration, and power consumption. To date there have been only a handful of implementations that have been able to meet the specification at a reasonable cost.

The level of performance is extremely difficult to attain, and requires the advanced digital signal-processing (DSP) algorithms that Excess Bandwidth has thrown at the problem. These algorithms, which are proprietary and remain under wraps, have determined the number and location of the taps required to perform the training, as well as the circuit tuning needed for optimum performance.

As a result of the increased number of taps and advanced algorithms, the amount of processing required demanded the use of an R4000, 32-bit RISC device running at 75 MIPS. This keeps the training time down to 20 to 30 s. To date, the typical solution has managed to survive by using a relatively low-end 8051 processor. But, that would be swamped by the calculations required here.

A key factor in the success of the Excess Bandwidth algorithms is the fact that they take into account the effects of both the amount and type of crosstalk present. The equalization is based on actual line measurements, and the running of an algorithm that provides for the best possible signal-to-noise ratio (SNR) at the output of the equalizer. Plus, the algorithms provide sophisticated "training" of the digital as well as the mixed-signal parts of the solution.

Training dynamically adjusts performance to the conditions of the line to which the solution is connected. This results in better overall system performance and provides a very high degree of interoperability. The end result is a system that always meets the 3.75-dB criterion, and in some cases performs to within 1 dB of the theoretical limits.

We can look at how each phase of the development performed on the worst-case test loops (Fig.1). That's the HDSL2 minimum test set versus the theoretical best performance, or Shannon Theory, and against the HDSL2 standard requirements. The tests show a 6- to 10-dB margin over other DSL systems. This can be exploited to either improve reach for a given data rate, or reduce the transmission power. Thus, the line's overall crosstalk is improved and its power dissipation is reduced.

A key decision that allowed the chip set to reach these performance levels was made early on. It was to develop a proprietary AFE (Fig. 2). This allowed the company to use its mixed-signal expertise to achieve several benefits. The first, an optimal tradeoff between the digital and analog elements of the solution, led to a more efficient partitioning of the analog and digital functions. This resulted in better silicon usage, lower power dissipation, and tighter coupling between the mixed-signal and digital elements.

Next, the embedded MIPS processor can be used to optimize the performance of the AFE stage in coordination with the tuning of the digital section. This brings about a high level of end-to-end system optimization in which the digital and mixed-signal subsystems are trained in parallel to match the observed loop characteristics. This couldn't have been achieved by using standard, off-the-shelf AFEs.

Fully compliant with the HDSL2/G.shdsl standard, the AFE also is configurable for either central-office (CO) or remote applications. It supports rates from 2.304 Mbits/s down to 192 kbits/s and has fully differential analog paths.

Both the AFE's 16-bit analog-to-digital converter (ADC), as well as the 16-bit digital-to-analog converter (DAC), sample at 2 MSamples/s. A DAC and filter for adaptive echo synthesis (AES) also is included.

The transmitter has programmable attenuation control (PAC) with a 16-dB dynamic range and 1-dB resolution for HDSL/G.shdsl-compliant power backoff. The receiver's programmable-gain amplifier (PGA) has a wide dynamic range of 32 dB and 1-dB resolution. The wide range is a key enabler for the algorithmic processing.

The AFE meets HDSL2 overlapped PAM transmission with an interlocking spectrum (OPTIS) power-spectral-density (PSD) mask when interfaced with the EBS720 digital chip. OPTIS is a noise-cancellation scheme that shapes the upstream and downstream transmit spectra for maximum performance in the worst-case noise conditions that occur in either end of the loop. The AFE includes an integrated voltage-controlled crystal oscillator and comes in a 64-pin TQFP.

The EBS720 digital processing end combines the PAM transceiver, framer, and the 512-state Trellis encoder and decoder (Fig. 3). Also included are the echo canceler, precoder, feed-forward equalizer, and decision-feedback equalizer. Supporting AES as well, it too meets ANSI HDSL2 and the emerging ITU G.shdsl standards. Further, it supports rates from 2.304 Mbits/s down to 192 kbits/s. A 16-level PAM with OPTIS transmit PSD mask is used for the T1 transport in the HDSL2 mode. Additionally, the device supports fall-back modes using 2B1Q line code, as in the case of SDSL. The PSD of the transmitted signal is programmable, a feature that allows it to reduce crosstalk and interference within the binder group.

A digital control bus included in the EBS720 allows communication with the AFE. This makes possible the tuning of settings within the AFE, while allowing for power cutback and other functions as well. Plus, the chip comes with an 8-bit parallel host interface and operates off 2.5 V. Packaging is in a 120-pin PQFP.

Both the EBS720 and EBS710 are made on a standard CMOS processor. The digital section is made on a 0.25-µm processor and has a power consumption of under 1 W, while the mixed-signal end is made on a 0.35-µm processor. This runs off 3.3 V and has, on average, a power consumption of 280 mW. These power figures are for full-rate, 1.5-Mbit/s HDSL2 operation.

Of course, the total power consumed also is a function of the line drivers, which varies widely for HDSL2 versus G.shdsl. The company expects its HDSL2 consumption to be in the range of several hundred milliwatts and under 400 mW for G.shdsl, for a total that weighs in under 2 W. The next-generation chip set will be under 1.5 W/port, including the line driver.

Price & Availability
The EBS720/EBS710 combination is priced at $35 each in quantities of 10,000. It's available now.

Excess Bandwidth Corp., 10670 N. Tantau Ave., Cupertino, CA 95014; Contact Joe Grady (408) 342-2730; fax (408) 255-0066; e-mail: [email protected]; www.exbc.com.

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