Electronic Design

Chip Twists ARM With Custom Logic

It's now possible to build custom ARM-based microcontrollers without high startup costs.

Single-chip solutions built with standard microcontrollers have been a boon to system designers who can access a wide selection of features, performance, and pricing. Unfortunately, to get the resources not found on standard parts, you need multiple chips. The usual alternative is a custom-built solution, but expertise and upfront costs often stifle this idea before it starts.

FPGAs typically are viewed as the solution to achieve this level of customization. In many cases, it's the most economical approach. But this tends to change as the number of parts needed per year rises.

Meanwhile, field-programmable approaches like Atmel's FPSLIC and Cypress Semiconductor's PSoC combine FPGAstyle logic with a hard processing core (see "Low-Power Microcontroller Combines With An FPGA Or PLD" at www.electronicdesign.com, ED Online 4771, and "Breaking News: Analog PSoC Family," ED Online 5936).

Atmel tips its hat with a new offering based on its metal-programmable (MP) block with up to 2 million FPGA-equivalent gates. This provides a customizable interface to a standard microcontroller platform, including standard peripherals. So, what's its edge? All programming is done at the factory.

The MP block logic maps well to FPGA lookup table (LUT) logic, allowing the CAP development platform to use a combination of a standard microcontroller and an FPGA. While such a combination can be used in a system, the CAP approach is much more economical in terms of cost and power. Plus, it can offer better performance in the custom gate block.

For example, a typical FPGA may consume 2 W in static mode, while a CAP package would fall in the 4-mW range. The difference in dynamic power consumption isn't as great, but it's still on the order of a factor of 10.

The approach definitely isn't suited for smaller projects. Typical quantities start around 50,000. Still, the non-recurring engineering (NRE) cost is fixed at $150,000, including samples.

CUTTING TO THE CORE
Designers can start with the ARM7 (Fig. 1) or ARM9 (Fig. 2) core. The ARM9 adds caching and memory mapping that are more suitable for larger, off-chip memories. This is reflected in the peripheral and interface complement.

The ARM7 platform, based on the ARM7TDMI core, features an on-chip oscillator that can reduce parts count. The on-chip ROM and RAM alone are sufficient for many applications, though the system does provide access to static memory and NAND flash. A typical multimedia application might use these for mass storage.

The DMA can handle the standard peripheral complement, which includes a range of serial interfaces, a USB interface, and an eight-channel, 10-bit analog-to-digital converter (ADC). The DMA controller has four dedicated bus masters for the MP block. It uses a six-layer bus that supports transfer rates up to 19.2 Gbits/s. The MP block can transfer data at speeds over 400 MHz. Also, an AMBA high-speed bus (AHB) matrix ties everything together. This includes peripherals implemented in the MP block.

The ARM9 platform uses a heftier processing core. It incorporates 11 buses that can deliver multiple, parallel data-transfer channels with a total on-chip bandwidth of 41.6 Gbits/s. The DMA controller also has hooks in the MP block, including three bus masters and a 12-layer bus. Thus, high-speed transfers up to 38.4 Gbits/s are possible for the peripherals implemented in the MP block.

The ARM9 standard peripheral and memory complement have a minor overlap with the ARM7 platform regarding timers and serial ports. The major difference is the addition of high-speed interfaces, such as USB, CAN, and Ethernet. The USB interfaces include the physical layer (PHY). There's also audio support with the AC'97 audio peripheral.

The number and complexity of the ARM9 platform's peripherals are higher, but the MP block is larger. This seems to be a reasonable tradeoff with internal memory, especially since most implementations will have off-chip memory. The on-chip memory controller supports double-data-rate (DDR) RAM in addition to static Compact Flash and NAND flash memory. Though the ARM7 platform lacks many of the standard peripherals of the ARM9 platform, both can design additional peripherals into the MP block.

CUSTOMIZING THE CORE
Designing custom logic for the MP block is still as complex as designing a custom system or logic for an FPGA. CAP removes the higher NRE associated with an ASIC or the higher cost and power requirements of an FPGA solution.

On the other hand, Atmel has a plethora of standard designs already available. This can significantly reduce the time and cost of designing a CAP chip. For example, creating a system that adds half a dozen or more high-speed USARTs is a relatively straightforward process. Standard chips with this many serial ports aren't available, but a CAP chip can easily handle it.

Because Atmel accepts standard RTL netlists, migration of existing designs is relatively straightforward. Development can be done using the AT91CAP9-DK development board, which includes an FPGA. Prototypes are typically available within 10 weeks of netlist delivery; for production quantities, it's usually within 16 weeks. The ARM cores are royalty-free, since their cost is folded in with the chips. Use of much of Atmel's IP library also is available at no charge.

Atmel's CAP initially targets its ARM microcontroller platforms. It will likely find use with Atmel's other microcontroller platforms, including the 32-bit AVR32.

Atmel
www.atmel.com

TAGS: TTI
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