Electronic Design UPDATE e-Newsletter Electronic Design Magazine - http://www.planetee.com May 7, 2003=============================
*************************ADVERTISEMENT************************** SPONSORED BY: TCI We offer a complete family of innovative, standardized and silicon proven PLL designs that now feature LockNow! (TM) Technology for very fast locking with minimal frequency overshoot. All PLLs are available in a range of frequencies, multiplication factors and functions in TSMC and UMC processes from 0.25um to 0.09um. Call (650) 691-2500 or visit http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACD0Ay **************************************************************** Today's Table of Contents: 1. Editor's View New Solutions For Embedded Controllers 2. News From The Editors * Low-Power, Pseudostatic RAMs Aim At New Cell Phones * DAA Shrinks 2400-Bit Modems * TCXO Draws Less Than 7 mW * Compiler Generator Takes On C++ * JVM Now Available For A One-Time Fee 3. Upcoming Industry Events * NanoBusiness Spring * SID2003 * 53rd Electronic Components Technology Conference * Supercomm * Sensors Expo & Conference * Design Automation Conference 4. Magazine Highlights -- April 28, 2003 issue * Cover Feature: Technology Report -- Interface Options Abound For MCU Networking * Leapfrog: Industry First -- Distributed Power: Novel Architecture Yields New DC-DC Building Blocks * Design View -- DDR Memories Place Tough Demands On Voltage Regulators Edited by John Novellino NEW: Go to www.elecdesign.com and participate in our first Quick Poll. The inaugural Quick Poll asks for your opinion of our newly redesigned Web site. ********************** 1. Editor's View -- Exclusive to Electronic Design UPDATE ********************** New Solutions For Embedded Controllers By David Bursky, Editor-at-Large Designers were treated to a veritable feast of advances in silicon, software, and system-level hardware at this year's Embedded Systems Conference (April 23-25) in San Francisco. One of the biggest challenges most designers admitted they faced was the ever increasing time it takes to develop their hardware and software solutions. The reason: the increasing complexity of the applications they are tackling. Microcontroller vendors try to counter this increasing development time by offering broader product offerings, hoping that one member of their product family will have a feature set close enough to match the user's requirements. Although that tactic provides the designer with a wide set of low-cost choices, it burdens the silicon vendor with the challenge of continually creating more family members until the product family becomes unwieldy. That has been changing, however, as electronic design automation tools, reusable blocks of intellectual property (IP), FPGA technology, and ASIC processes get better and let designers leverage all of them simultaneously to rapidly develop new system-on-a-chip solutions. Enhanced design tools enable engineers to more quickly define and craft the logic for new embedded processors, and IP libraries save valuable design time, while FPGA technology permits faster prototyping and even limited to mass production of various solutions. Advances in ASIC processes, meanwhile, allow ever more complex subsystems to be squeezed onto a small chip. Mask and other development costs of a full ASIC solution can get out of hand, though, unless the final chip will sell in the millions of units per year. So there is a tug of war, of sorts, festering between off-the-shelf microcontrollers, the use of the somewhat inefficient FPGA approaches, and full-ASIC approaches. A fourth design option, which is still in its embryonic stage, is the use of what a few companies call an ASIC platform. Several architectural approaches loosely fall into this "platform" category, but they all claim shorter development time than a full ASIC, lower nonrecurring engineering costs than full ASICs, and a more area-efficient design than FPGAs (see "Fast Turnaround ASIC Platforms Speed Complex Chips To Market," Electronic Design, February 17, 2003, p. 40). This emerging area will leverage the best aspects of the various technologies to provide designers with new options for crafting custom solutions. The challenge will be to provide the solutions cost-effectively and to rapidly meet the ever shorter time-to-market demands. Contact David Bursky at: mailto:[email protected] To discuss this article, go to http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ05cg0An ********************** 2. News -- From The Editors ********************** ***Low-Power, Pseudostatic RAMs Aim At New Cell Phones Targeted at 2.5 and 3G wireless handsets and other portable applications, the CellularRAM family of low-power, pseudostatic memories has been jointly defined and released by Cypress Semiconductor Corp., Infineon Technologies AG, and Micron Technology Inc. The memories offer a 16-bit data path and come with either an asynchronous or burst interface. The 32-Mbit version operates at clock rates of up to 104 MHz and has an initial latency of 70 ns. The chips can achieve a peak bandwidth of up to 208 Mbytes/s (1.5 Gbits/s). The memories' cost/bit ratio will be lower than current solutions, and they will be drop-in compatible with asynchronous low-power SRAMs. Micron is currently sampling 32- and 64-Mbit memories, with full production expected next quarter. Infineon is sampling the 32-Mbit device and plans to go into full production next quarter. Cypress plans to sample the 32-Mbit chip in the first half of 2004. A 128-Mbit device is planned for late in 2004. Additionally, Infineon plans to offer CellularRAM products in known-good die wafer formats so that memory subsystems can be tuned to specific application requirements. For more information, visit http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACE0Az ***DAA Shrinks 2400-Bit Modems Silicon Laboratories' third-generation silicon data access arrangement (DAA) creates an embedded 2400-bit/s modem that reduces bill-of-material costs, parts count, board area, and power consumption compared to existing solutions. Housed in a 16-pin SOIC, the Si2401 ISOmodem is part of a two-chip set that additionally includes the Si3010 programmable global line interface, also in a 16-pin SOIC. Chip-set pricing begins at $7.33 in lots of 10,000. The bill-of-materials cost is approximately $0.50 for the external components, not including the pc board. Power consumption for the Si2401 is less than 30 mW. Contact Silicon Laboratories at http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACF0A1 ***TCXO Draws Less Than 7 mW Drawing less than 2 mA (under 7 mW from a 3.3-V supply), the surface-mountable ER family of temperature-compensated crystal oscillators (TCXOs) is a good fit for battery-powered applications. The oscillators develop a user-specified output of 12 to 19.68 MHz and are compatible with HCMOS and transistor-transistor-logic families. Jitter (phase noise) is a low -125 dBc/Hz at a 1-kHz offset. Additionally, they feature mechanical and electrical frequency trimming of ±3 ppm and ±4 ppm, respectively. Long-term aging is typically less than ±1 ppm/year. The oscillators maintain ±2.5-ppm frequency accuracy from -30°C to 70°C. Based on hi-Q quartz crystals, they're available on tape and reel for automated circuit-board assembly. The devices measure 11.4 by 9.6 by 2.5 mm. They cost $4 each in OEM lots and are available from stock to four weeks. Contact MF Electronics Corp. at http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACG0A2 ***Compiler Generator Takes On C++ The CoSy 2003 compiler generation package from ACE Associated Compiler Experts has added C++ support. Developers can use CoSy 2003 to create C++ compilers for a broad range of DSP, NPU, RISC, VLIW, and 8/16-bit processors with minimal work. The new version provides flexible bit-field support and the aiSec graphical visualization package. New optimizations include software pipelining and support for parallel execution units. Pricing starts at $250,000. Contact the company at http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACH0A3 ***JVM Now Available For A One-Time Fee PERC, the clean-room J2SE-class Java virtual machine, is now available royalty free. NewMonics' new pricing policy has deployment packages starting at $30,000 per target architecture. Source code is optionally available. It will be interesting to see if other vendors in the JVM space follow this pricing model. Contact NewMonics at http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACI0A4 ********************** 3. Upcoming Industry Events ********************** May 11-13, NanoBusiness Spring, New York Marriott Financial Center, New York. Produced in association with the NanoBusiness Alliance, the show will feature presentations, demonstrations, networking, and business deals covering the emerging business of microsystems and nanotechnology. http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0plc0Ar May 18-23, SID2003, Baltimore Convention Center, Baltimore, Md. Society For Information Display: International Symposium, Seminar, and Exhibition. The industry's premier gathering for display technology. Symposium: May 20-22; seminars, applications, tutorials, and short course: May 18-23; exhibition: May 20-22; business conference: May 19. http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ08CL0Ar May 27-30, 53rd Electronic Components Technology Conference, New Orleans, La. Organized by the IEEE/CPMT (www.ieee.org), the conference focuses on electronic components with a concentration on packaging. It includes sessions on optical and fiber-optic components. http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ08CM0As June 1-5, Supercomm, Atlanta, Ga. The show includes networking, communications, broadband, and wireless sessions. (800) 873-7277 or http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ0BACJ0A5 June 2-5, Sensors Expo & Conference, Chicago, Ill. (co-located with International Robots & Vision Show and the Industrial Fastener & Forming International Exhibition & Conference) Sponsored by Sensors Magazine. Contact [email protected] for registration and [email protected] (Eastern U.S. and Canada) or [email protected] (Western U.S. and international) for exhibits. June 2-6, Design Automation Conference. Anaheim, Calif. DAC has long been the EDA industry's premier venue for product announcements, technical presentations, and networking. http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ07w50AL Postponed: Due to the epidemic of severe acute respiratory syndrome (SARS) in Asia, the Taipei Power Forum & Exhibition, scheduled for Nov. 3-5, has been postponed. No rescheduled date has been announced. ********************** 4. Magazine Highlights ********************** In case you missed them, here are some of the high points of our most recent issue, April 28, 2003. * Cover Feature: Technology Report -- Interface Options Abound For MCU Networking Microcontroller connectivity is growing as additional standard MCUs sport one or more network interfaces. * Leapfrog: Industry First -- Distributed Power: Novel Architecture Yields New DC-DC Building Blocks BGA-style dc-dc building blocks implement a new distributed power architecture that promises higher performance and lower cost. * Design View -- DDR Memories Place Tough Demands On Voltage Regulators The introduction of double-rata-rate (DDR) memory has afforded a quantum leap in performance for commercially available desktop and portable computers. For the complete Table of Contents, go to http://lists.planetee.com/cgi-bin3/DM/y/eQoS0DJhUf0EmQ03Hf0AJ==================================
Editorial: Lucinda Mattera, Associate Chief Editor: mailto:[email protected] Advertising/Sponsorship Opportunities: Bill Baumann, Associate Publisher: mailto:[email protected]=========================
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