Electronic Design

Embedded Hardware> Serial Migration Hits Full Stride

The year 2004 sets up as an interesting period for the PC. In the second half of the year, the long-anticipated launch of the first PCI Express products will take place, marking the most significant change in PC architecture in almost 10 years. This remarkable event follows in the footsteps of several other major serial bus transitions, including USB, 1394, and most recently, Serial ATA.

PCs have come full circle with respect to I/O. The first serial bus, or RS-232 port, was utilized as the attach point for the slowest of peripheral devices, while the much faster parallel port was reserved for the early era's high-speed components. By nature, the original serial port was limited in bandwidth when compared to its back-of-the-box neighbor, the parallel port. This was due simply to the fact that a single bit was transferred in each direction at a given time versus the eight-plus bits of the parallel port.

As frequencies progressed over the years and eventually surpassed the 1-GHz level, skew management of independent signals on the wider buses became a significant challenge. Engineers were forced to create worst-case "windows of time" to allow for the last bit of a given parallel access to reach the register before being latched by the single reference clock. Designers were forced to extend the cycle of the clocking mechanism and slow down the overall transfer. This sharply contrasts what was being done with serial using a dedicated clock for each bit.

In the new serial world, the clock is encoded with the data bit on a differential pair of wires and then decoded on the back end (8b/10b encoding scheme). This allows for signals to be run at speeds only limited by the physical characteristics medium. If a design eventually becomes limited by, say, the use of copper, a simple transition to a new physical layer (such as optics) can take place. In addition, if a wider datapath is necessary, multiple individual serial ports, each with their own encoded reference clock, can be strung together and meshed at a higher layer as a larger data word.

Today, the limitations are certainly reduced as the industry moves to multi-gigabit serial buses with features not seen in previous parallel designs. These new buses will manifest themselves throughout the PC, encompassing the storage system (Serial ATA and Serial SCSI), the graphics system (PCI Express), the chip-to-chip interconnects (PCI Express), I/O modules (ExpressCard), and, of course, the already-supplanted I/O (USB 2.0 and 1394). Furthermore, the user community will benefit from new use opportunities inherent in long-running serial architectures like hot-plugging, external or out-of-box signaling, and split-system concepts. Indeed, 2004 promises to be an interesting year.

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