Electronic Design
Field-Programmable I/O Augments 8- And 32-Bit Microcontrollers

Field-Programmable I/O Augments 8- And 32-Bit Microcontrollers

Thanks to its reconfigurable peripherals, the original programmable system-ona- chip (PSoC) from Cypress Semiconductor is one of the major microcontroller advances of the past decade. However, its proprietary 8-bit microcontroller limited its use in many higher-end applications. The release of the PSoC 3 (based on the 8051) and the PSoC 5 (based on the Cortex-M3), along with some major changes in the reconfigurable peripherals, revises the equation entirely.

The high-performance, 67-MHz 8051 processing core in the PSoC 3 opens the PSoC architecture up to a host of 8051 developers and legacy applications. Cypress Semiconductor’s 8051 core is also significantly more powerful than the original PSoC, now called PSoC 1, giving developers a much needed boost in computational power. The PSoC 1 remains an alternative. But the faster, more power-efficient PSoC 3 will likely garner the bulk of new designs not relegated to the PSoC 5.

The 80-MHz ARM Cortex-M3 has been a popular 32-bit platform for microcontrollers in recent years. A long-awaited addition to the Cypress product line, it gives developers yet another performance level for the PSoC architecture. It has a surprising set of low-power modes, making it a challenger even for the PSoC 3.

If the processor cores were the only feature that the PSoC architecture had to offer, then Cypress Semiconductor’s releases would simply get lost in the horde of competing 8051 and Cortex-M3 products. Luckily, their configurable peripherals let these PSoCs stand out from the crowd.

All of these PSoC chips include a processing core and memory, plus a collection of configurable digital and analog processing blocks (Fig. 1). This time around, each universal digital block (UDB), up to 24, includes eight macrocells, 16 product terms, a data path/interconnect, and control and status registers. The UDBs are a highlight of the physical layout, but the grouping doesn’t restrict how the components can be connected.

This effectively makes the PSoC a microcontroller with a field-programmable component array (FPCA). The FPCA is more powerful than a programmable logic device (PLD) but less flexible than an FPGA. The FPCA has similar restrictions with respect to interconnects within an FPGA, but issues typically don’t arise until utilization approaches 100% or interconnect complexity is high.

Unlike FPGAs, the typical way to configure the FPCA is to select from a menu of predefined peripherals such as serial ports. Each uses some number of components (macrocells, registers, etc.). This way, a UDB may include one or more peripherals, and a peripheral may span multiple UDBs. In general, a PSoC developer doesn’t have to worry about the details, as long as the number of required components is less than that supplied by the desired chip.

The big change is the redesign of the PSoC digital and analog blocks, which are significantly more powerful. It’s possible to implement things like a state machine and lookup table. Likewise, analog and digital peripherals can be linked together for operation without program intervention. This includes sophisticated configurations such as motor control with overvoltage detection and emergency shutoff.

The analog components are impressive. The 12-bit successive approximation register (SAR) digital-to-analog converters (DACs) operate at speeds up to 1 Msample/s. There are 6- and 12-bit filters, and the analog-to-digital converters (ADCs) have up to 20-bit resolution. On-chip precision voltage sources have a 0.1% precision. Operational amplifiers and amplifiers support a range of configurations. The analog components can be connected to build signal chains. CapSense touch-sense detection is included as well.

Developers can choose a mix of peripherals such as a lot of serial ports as long as the chip has enough resources. The product line has chips with varying numbers of UDBs in the same fashion, as the amount of flash and SRAM varies. Higher-end chips have more of everything. The chips also have a 24-channel direct memory access (DMA) that can be linked to any peripheral.

The PSoC 3 chips currently support up to 64 kbytes of flash, 8 kbytes of error correction code (ECC), 8 kbytes of SRAM, and 2 kbytes of EEPROM. The PSoC 5 chips currently support up to 256 kbytes of flash, 32 kbytes of ECC, 64 kbytes of SRAM, and 2 kbytes of EEPROM.

The chip’s ability to connect any pin to any component in the array allows for an amazing amount of flexibility. Likewise, the ability to hook into almost any signal within the array makes debugging easier. For example, a set of internal signals can be exposed on unused pins. This approach is unprecedented in anything short of an FPGA.

Other new PSoC features include four voltage groups for I/O pins. This enables the chip to handle its own level-shifting chores. Some pins could be used for high-voltage devices, while others use a lower voltage. Most microcontrollers support a single voltage for their I/O. Also, an on-chip voltage boost permits the chips to run with as little as 0.5 V from single-battery operation while maintaining the accuracy of the analog peripherals.

Access to the soft peripherals, their design, and configuration is provided through the PSoC creator integrated development environment (IDE) (Fig. 2). It uses a familiar graphical schematic design system. Peripherals are chosen from a library, and new peripherals can be constructed. Primitive peripherals such as AND and OR logic gates allow most application peripheral sets to be created using the schematic design approach.

Although most developers won’t look under the hood, Verilog is the underlying definition mechanism for peripherals. It’s now available to developers, unlike earlier versions of the PSoC that only permit selection of predefined peripherals.

Continue to page 2

The use of Verilog to define new peripherals is more restrictive than most FPGA environments. Likewise, FPCA components are less numerous and more functional, so migrating an FPGA Verilog design of any sophistication to PSoC is unlikely to work.

On the other hand, some amazing things can be done using Verilog and PSoC. It’s possible to start from an existing peripheral design and modify it. This includes the configuration dialog box accessible from the PSoC Creator associated with each peripheral that allows customization. PSoC Creator also handles signal routing. Almost any signal can be connected to a pin, providing flexible board layout.

The IDE is integrated with a number of compilers to handle the range of PSoC processor architectures. The PSoC 3 support includes the Keil CA51 C compiler with no code size limits, though it only works with PSoC parts.

An integrated debugger works with all three platforms and the various development kits currently available. This includes the $49 PSoC 3 Starter Kit as well as the more flexible PSoC Development Kit (Fig. 3). The module socket accepts the PSoC 3 or PSoC 5 modules that come with the kit or a PSoC 1 module.

The new PSoC chips and design software give developers significantly more powerful platforms with more peripheral design flexibility than ever before. With this approach, a single chip can address a wide range of applications.



Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.