Electronic Design

Flash Memory Cell Uses "Mirrors" To Double Its Capacity

A novel memory cell architecture dubbed MirrorBit lets flash memory cells hold twice as much data as standard flash cells without compromising performance or data integrity.

Developed by Advanced Micro Devices, it places two bits of data in each cell by storing electrons in two physically distinct locations in the same nonconductive nitride layer. By storing the bits on opposite ends of the nitride layer, each half of the memory cell appears to "mirror" itself as if an imaginary line is drawn vertically through the center of the cell.

Each bit can be read or programmed independently, and each is programmed using the full electron charge. Other multibit per cell schemes divide the charge into four sublevels to represent the two bits, requiring careful control of threshold settings for the comparators to sense the levels. The overhead for sensing the levels also needs a little more time, so the multilevel charge schemes typically cannot access data as fast as the MirrorBit cells can. Multilevel-cell-based chips, then, have slightly slower access times.

The basic memory cell in the MirrorBit flash starts with an MOS transistor. The nonconductive storage element, created with a specially formulated nitride deposition, is above the gate region. The insulated gate electrode is above the storage element. Because the nitride storage region is nonconductive, charge stored in the material will remain in place, so it can be very localized. In AMD's approach, two charge regions are formed to represent each data bit at each end of the nitride storage element (the left and right bits).

The transistor operates symmetrically. Source and drain regions can be electrically interchanged. This is key to how the two charge regions are formed and read during memory operation. By biasing the source, drain, and gate with the appropriate levels, one charge location can be programmed by injecting electrons. By reversing the source and drain biasing, the second charge location can be programmed. To read the data from the cell, the gate bias is changed, and the bias levels on the source and drain are set appropriately to read from one of the two localized charge sites. To read the second bit in the cell, just the source and drain bias levels must be reversed.

This radically different approach enables one transistor to act like two, doubling storage capability. The storage cell's physical design is considerably smaller than the standard flash memory cell. Close to 50 MirrorBits can be stored in the area occupied by 16 standard single-bit flash cells, almost tripling the memory chip capacity. Compared to multilevel cell storage schemes, the MirrorBit cells provide about 50% more capacity.

Used in an array, the cells' physical layout is much simpler and therefore easier to manufacture. Fewer process steps are needed, so more wafers per month can be moved through the fabrication process. The combination of doubling to tripling the storage capacity and simpler manufacturing process will yield a lower cost per chip. So, the NOR-style memory arrays built with the MirrorBit approach will compete with the high-density NAND-based word-sequential flash memories.

Erasing the cells is also simple. With the proper biasing, designers at AMD can use the company's proven negative-gate-erase approach. Negative-gate and common positive voltages are used during erasure, which is similar to the approach used in conventional single-bit flash memories. The left and right bits of a MirrorBit cell are always in the same sector, so an entire MirrorBit cell is erased during a sector- or chip-erase operation.

The MirrorBit memory cells will be incorporated into a full family of flash memory chips, ranging from 16 Mbits to 1 Gbit. The chips will be pin-compatible with AMD's existing Am29LV family of single-bit-per-cell flash devices.

The first device, a 64-Mbit chip, will access in 90 ns and offer a 100-ms sector erase time (64-kbit sector) and a standby current drain of just 1 µA. A 20-year data retention capability is guaranteed. The 64-Mbit chip will also incorporate a high-speed (25-ns) page-mode read capability and a high-throughput 6-µs/word programming speed thanks to an on-chip page buffer. It will cost just $7.95 each in quantities of 10,000.

Advanced Micro Devices, www.amd.com; (408) 732-2400.

See associated figure

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish