Electronic Design

Hardware Directory: Architecture Targets Multiprocessor System-On-A-Chip Applications

Two processors can work better than one when they're tuned to a particular application area. Tensilica's new Xtensa-V architecture makes this possible for any number of processors in addition to providing improvements in a single-processor environment.

Tensilica's approach leads the pack in terms of flexibility. Its TIE (Tensilica Instruction Extension) language makes implementation of custom instructions significantly easier. The development tools generate all the necessary support without the need to work with register transfer language (RTL) design. The Xtensa configuration system also permits customization of many more aspects of the processor, from register files to cache design.

Most of the enhancements in the Xtensa-V architecture target multiprocessor designs. Tensilica customers frequently implement three or four Xtensa processors, but they're often unique. Improved interprocessor communication lets processors work together better. For example, incoming read/write requests let one processor access a peer's local memory. Simple things like a unique processor ID enable systems to start running immediately instead of having to be configured by a central processor. Extensive compiler improvements include cross file inlining of functions. The support for vector/single-instruction, multiple-data (SIMD) instructions has been enhanced as well.

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See associated figure.

WHAT'S NEW
  • Architecture tuned for multiprocessor configuration
  • Multicycle capability on Xtensa Local Memory Interface (XLMI)
  • Incoming read/write request
  • Incoming read/write request
  • Writeback cache option
  • Supports fault tolerance
  • Processor ID register
  • Enhanced C++ compiler
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