Electronic Design

HyperTransport: The Ties That Bind

HyperTransport is a generalized point-to-point I/O interface that's been enhanced to support cache coherency by AMD. It's used for I/O with AMD's Athlon chips. It's also used for I/O and non-uniform memory access (NUMA) support in AMD's Opteron chips, which lets designers create a multiple-chip system without any intervening chips like the memory host controllers found in Sun and Intel multichip solutions.

Programming issues tend to pop up, though, as the number of hops between chips goes above one and the frequency of multihop memory accesses is high. If locality of reference is high, making the latter low, then the number of hops becomes irrelevant. Unfortunately, this is applicationand software-environment-specific. So like other multicore architectures, the approach won't be optimal in all instances. Of course, it may be good enough, and the ability to link large numbers of multicore chips together will typically result in economical, high-performance solutions.

See Associated Figure

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish