Heralded as the industry's first and only fully integrated, hierarchical, timing-driven system-on-a-chip (SoC) design system, the Integration Ensemble (IE) hierarchical integrated circuit (IC) implementation tool represents the next generation of the company's SP&R (synthesis/place-and-route) software packages. IE runs from register transfer level (RTL) to GDSII on a single database with single synthesis, placement, timing, and routing engines.
Built on an ultra-high capacity and high performance SoC database, the tool is capable of handling designs of more than 25 million gates and to process geometries of 0.12 µm and below. Other features include support for multi-supply designs, hierarchical signal integrity prevention and analysis, and full chip integration and assembly. Price for a time-based license starts at $600,000.
Company: CADENCE DESIGN SYSTEMS INC.
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