Electronic Design

ISSCC 2002 Report In Print: Analog & Mixed Signal

New architectures push ADCs to higher speeds and resolutions, as they tap mainstream CMOS.

A greater need for faster and better data converters continues to motivate designers. To keep pace with the demands of emerging applications, data-converter developers continue to innovate newer architectures and clever circuit techniques, as technical presentations at this year's International Solid-State Circuits Conference (ISSCC) show, especially in the area of high-speed analog-to-digital converters (ADCs).

Several papers in Technical Session 10 on "High-Speed ADCs" will set new benchmarks in conversion rates for 8- and 6-bit CMOS ADCs. Combining innovative architectures and process advances, these presentations will extend the state-of-the-art in Nyquist ADCs with record-breaking speeds at lower power dissipation, using mainstream CMOS processes.

Toward that goal, researchers from Agilent Technologies have realized a 4-Gsample/s 8-bit ADC in conventional 0.35-µm CMOS. This was achieved by joining massive parallelism with comprehensive calibration of input voltages and timing signals.

The Agilent ADC boasts an accuracy of 6.1 effective bits at 1-GHz inputs (Paper 10.1). Until now, such high-speed ADCs for real-time high-bandwidth waveform capture were implemented in bipolar or III-IV processes. In Agilent's current-mode pipeline architecture, 32 time-interleaved pipelined ADCs are combined on one chip with offline calibration.

To permit the use of small CMOS devices, this architecture employs a reduced-radix scheme. Each pipeline ADC is followed by a radix conversion block that converts the 12 reduced-radix bits into 8 binary bits. Output multiplexers combine the data into four output streams, each delivering 1 Gsample/s (see the figure).

In this pipelined design, the 32 track-and-hold (T/H) circuits operate sequentially at 250-ps intervals. The 32 interleaved clocks offer 1.1-ps (rms) accuracy to drive 32 current-mode pipelined ADCs. The 250-ps edge spacing is created by a delay-locked loop (DLL) locked to the input clock, which runs at 500 MHz. Consuming 4.6 W at 3.3 V, the 8-bit ADC occupies a 7.14- by 4.04-mm2 area.

At Philips Research labs, Eindhoven, the Netherlands, converter designers have incorporated an averaging termination technique. It overcomes problems that arise from using resistor averaging in interpolating flash ADCs. Implementing the proposed averaging termination circuit (Paper 10.2), Philips will unveil a 1.6-Gsample/s, 6-bit flash ADC in 0.18-µm CMOS. That's nearly three times faster than any present designs. This ADC achieves 5.7 effective number of bits (ENOB) at dc and maintains 5.0 ENOB at up to 660 MHz. It dissipates 328 mW powered by 1.95-V analog and 2.25-V digital supplies.

More ADC Advances
Session 10 also highlights works from the University of California, Shizuoka University, and Infineon Technologies AG.

At the University of California, Davis, researchers have developed a time-interleaved pipelined ADC that implements digital background calibration to overcome the effects of mismatch errors without affecting the signal spectrum (Paper 10.4). Researchers employ adaptive signal processing to attain true background calibration with neither special calibration intervals nor calibration signals. The proposed scheme has been implemented in a 10-bit pipelined ADC that offers a conversion rate of 120 Msamples/s.

At Shizuoka University, Hamamatsu, Japan, designers have developed a pseudodifferential architecture for pipelined ADCs. Using this novel scheme, the researchers have pushed power consumption of a 10-bit, 30-Msample/s pipelined ADC down to a record low of 16 mW at 2 V (Paper 10.5).

Likewise, maximum differential and integral nonlinear (DNL and INL) performance is said to be less than 0.4 and 0.5 least-significant bit (LSB), respectively, at an input of 2 MHz. The unique design allows the use of simple wideband cascade amplifiers with relatively small bias current, while maintaining high power-supply rejection and tolerance to crosstalk from digital circuitry. The chip is implemented in 0.3-µm CMOS.

Similarly, scientists at Infineon Technologies' Microelectronics Design Centers in Villach, Austria, have exploited a nonbinary algorithm to extend the speed of a successive-approximation ADC, while retaining the inherent advantages of small area and low-power dissipation (Paper 10.6). Infineon's researchers will disclose a 10-bit, 20-Msample/s nonbinary successive-approximation ADC in 0.13-µm CMOS that consumes 10 mA at 1.2 V.

Oversampling ADCs For Wireless
To cope with the stringent demands of converting IF to digital form in forthcoming wireless systems, designers are tapping the benefits of multibit, multi-order delta-sigma (Δ-Σ) architectures. Several papers in Session 13 on "Oversampling ADCs" focus on such activities, leading to a new generation of high-bandwidth, high-resolution ADCs with high levels of integration and performance at low power consumption.

Notable developments include one from Analog Devices (Paper 13.2). In this work, researchers combined a multibit bandpass Δ-Σ ADC with continuous-time LC and active RC resonators, and a switched-capacitor resonator. The result is a high-performance ADC with an on-chip mixer for dual-conversion superheterodyne receiver applications. It consumes only 50 mW and offers an unprecedented 90-dB dynamic range at an oversampling ratio of 48 over a 333-kHz band from 10- to 300-MHz input.

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