Electronic Design

Java Processors

  Jazelle Espresso Lightfoot
Company ARM Aurora VLSI Digital Communications Technologies
Processor type Internal extension to CPU 32-bit Java CPU 32-bit Java CPU
Dispatch method On memory address Executes bytecodes Executes bytecodes
Registers Uses host CPU registers Stack (eight 32-bit registers) Stack (eight 32-bit registers)
Bytecode coverage 60% (140 of 234) 90%+ (14 with software assist) 100%
Distribution As part of ARM processor IP As IP core As IP for FPGAs, ASICs
Number of gates 12,000 (Not available) 25,000
Clock rate 80 to 200 MHz 140 to 400 MHz 40 MHz
Miscellaneous Extensions for ARM7, ARM9 Two-way superscalar, five-stage pipeline 8-bit program memory


Jazelle Extension
Another way to speed Java execution on a standard RISC architecture is to extend the architecture itself, to directly execute Java instructions. ARM designers added a new Java instruction set to the classic ARM architecture. The Java ISA is executed in a Java mode, which is entered on a branch. In the Java mode, the CPU executes Java bytecode instructions. Bytecodes are fetched and decoded in two stages, compared to Thumb's single stage.

Jazelle delivers eight times the performance gains of Java software JVM. Jazelle does 6.0 Caffeine Marks per megahertz and takes roughly 12,000 gates. An ARM 926EJ delivers 1000 Caffeine Marks at 200 MHz. Jazelle is implemented as an additional path in the instruction-stream decode. It extends the five-stage ARM9 pipeline to six stages. www.arm.com.
See associated figure.

Espresso
Aurora VLSI's Espresso Java processor is a superscalar RISC engine. The CPU has two operational units, each with an integer and a floating-point processing unit. The core delivers 32,500 Caffeine Marks at 200 MHz and 60,000 CMs at 400 MHz. Its peak execution rate is eight Java instructions/cycle. Espresso supports a 32-bit 128-entry stack. It has 32 to 256 on-chip registers (configurable) and supports 16k to 32k I and D caches with 64-bit interfaces.

Aurora also fields a low-power core, DeCaf. Both cores are available in versions that also execute C and C++. DeCaf power consumption is around 2.0 mW/MHz (0.18 µm). DeCaf delivers 20,000/35,000 Caffeine Marks (200/400 MHz). It executes four instructions/cycle or seven bytecodes/cycle. http://vodka.auroravlsi.com.
See associated figure.

Lightfoot Java CPU
Another way to speed Java execution is to directly execute bytecodes in hardware. This design tactic eliminates the interpreter and keeps Java's small program memory footprint. Digital Communications Technologies' Lightfoot is a direct-execution Java CPU with a one-to-one mapping between bytecodes and lightfoot instructions. The 32-bit Harvard RISC CPU provides stack execution for both Java and C. It implements an eight-register-deep stack, with extensions to data memory.

The ALU incorporates a 32-bit barrel shifter and a 2-bit step multiplier. (It takes 16 cycles for a 32-bit multiply.) The CPU implements an 8-bit "bytecode" instruction memory interface (24-bit address). Data memory is supported by a 24-bit address, 32-bit memory path. The Java core supports J2ME, JavaCard, and C. Also, the core is extensible; users can add additional instructions. The soft core is available as a VHDL IP for ASICs and for Xilinx FPGAs. On a Xilinx Vertex-II FPGA, the core requires 1710 CLBs. The core supports J2ME, JavaCard, KVM, and JINI. www.dctl.com.
See associated figure.

  JVXtreme JStar XPRESSOcore
Company InSilicon Nazomi Communications Zucotto Wireless
Processor type Java Coprocessor Java Preprocessor 32-bit Java Processor
Dispatch method Via coprocessor instr. On memory address Executes Java bytecodes
Registers Uses CPU registers Uses host CPU registers Stack
Bytecode coverage 87 most common byte codes 70% (160 of 227) All bytecodes except JVM, file, and interrupt management
Distribution IP (Verilog) As IP IP core
Number of gates 35k 30k 60,000
Clock rate 200 MHz 50 MHz 150 MHz
Miscellaneous ARM9 coprocessor, RTL core Coprocessor for ARM, MIPS, Lexra 22.5 Caffeine Marks/MHz


JVXtreme Accelerator
Most RISCs support a coprocessor interface. That can be used to hook up to a Java coprocessor. The JVXtreme Java coprocessor accelerator from InSilicon delivers Java sustained performance on the order of 15× over an interpreter, and a peak 55× gain. It executes 87 of the most commonly used Java byte codes in hardware. www.insilicon.com.
See associated figure.

JStar
Nazomi Communications' JStar works with a range of processors, such as ARM, MIPS, and Lexra, and can be customized for others. JStar's Java translation mechanism is automatically invoked whenever the main processor's instruction pointer falls within a specified memory address range. Java code is simply placed in this memory and can be called directly. JStar uses the processor's registers, including the stack registers, to handle calls just like native code. www.nazomi.com.
See associated figure.

Xpresso
CISC processors are not dead. Zucotto Wireless' Xpresso cores implement a Java CISC processor. The core and microcontroller family include the Xpresso 100 microcontroller, and the Xpresso 120 and 150 cores with a five-stage pipeline engine that directly executes most Java bytecodes in one cycle. Most of the VM instructions are directly done in hardware. For higher performance, 16-kbyte I and D caches can be added. The hardware also in-cludes a local variable and stack cache.

The XPRESSOcore 150 includes a 32-bit data bus and supports integer types up to 64 bits. It implements static and dynamic branch prediction. The ALU includes a 16-bit modified Booth multiplier. The processors support low-power, wireless operation. The Xpresso 100 delivers 9 Caffeine Marks/MHz, at 40 MHz. It has a Bluetooth baseband controller and optional Bluetooth upper stack, five 16-bit timers, two USARTs, and a codec port. www.zucotto.com.
See associated figure.

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