Electronic Design
Many Core Systems Handle Network Processing Chores

Many Core Systems Handle Network Processing Chores

Tilera is now delivering its 16- and 36-core Gx chips and development platforms. The 40nm many-core TILE-Gx36 can handle L2/L3 packet forwarding at 40 Gbit/s while using under 25W of power. This is under 0.5W per core. The array of 64-bit VLIW cores is surrounded by peripheral and memory interfaces (Fig. 1). The platform targets network processing with tools like the MiCA engines include 20 Gbit/s crypto support. They can also compress/decompress packets at 10 Gbits/s. The programmable mPIPE Ethernet front end provides partitioning and load leveling support.

Fig. 1: TileGX many-core architecture has a fabric that ties cores together. The mPIPE network interface provides partitioning and load leveling support.

Share memory access is provided by four 64-bit DDR3 controllers with ECC support. These deliver over 500 Gbits/s of memory bandwidth. The three PCI Express Gen 2 x4 interfaces can act as a host or device. The network interfaces can be x8 10 Gbit/s, x32 1 Gbit/s or a pair of 40 Gbit/s ports.

Each core (Fig. 2) has a three-way pipeline that runs up to three instructions per cycle. The core has a 32 Kbyte L1 instruction cache and 32 Kbyte L1 data cache. It also has 256 Kbyte L2 cache.

Fig. 2: Each TileGX core has its own Terabit Switch that handles multiple serial interfaces.

The cores pack quite a computational punch. The TILE-Gx36 has a EEMBC CoreMark is over 165,000. The cores have DSP and SIMD instructions. Floating point is handled in software but VLIW instruction support completes operations in five cycles.

Tilera's iMesh network actually consistts of multiple interconnects. Tilera's DDC (Dynamic Distributed Cache) interconnect handles cache coherency. DDC supports hardware parititioning allowing cores to be grouped into isolated compute islands. Other interconnects handle memory and communication operations including TileDirect coherent I/O support.

The Gx chips support an environment called Zero-Overhead Linux (ZOL). ZOL is a tickless Linux environment that can be used for embedded applications like packet processing. It provides access to Linux APIs but runs a dedicated task more efficiently than on with a conventional operating system.

Tilera is also delivering development and evaluation platforms like the TILEncore-Gx (Fig. 3). The TILEncore-Gx is a PCIe Offload NIC with a x8 PCI Express interface. The host has network device drivers that access the board via the PCIe interface.

Fig. 3: The TILEncore-Gx is a PCIe Offload NIC with a x8 PCI Express interface.

1.2 GHz TILEncore-Gx has two DDR3 SODIMM slots. The TILEncore-Gx 16- version has 4 Mbytes installed and the 36-core version has 8 Gbytes installed. Both have four 1G/10G SFP/SFP+ Ethernet ports. There is also a USB 2.0 port and SATA 2.0 controller. The on-board software can handle security, transcoding and other packet processing chores.

TileGX mezzanine cards house a 16- or 36-core processor (Fig. 4). They also have four DDR3 sockets. They are designed to plug into the TILEmpower-Gx (Fig. 5) and Liberty-Gx rack mount systems.

Fig. 4: The TileGX mezzanine card has its own on-board DDR3 DRAM.

The TILEmpower-Gx is a 1U 40G appliance. It has a TILE-Gx36 and four 10G network ports. It comes with Manycore Development Software V4.0. The system comes with an IPMI module.

Fig. 5: The TILEmpower-Gx is powered by a mezzanine card and has a x8 PCIe expansion.

The 1U Liberty-Gx uses 4 mezzanine cards. With TILE-Gx36 chips, the Liberty-Gx has 144 cores. It is essentially four TIMEmpower-GX systems in one but with fewer expansion options per board. It also has IPMI support. Each mezzanine card has a matching 4 port, 1G/10G Ethernet card.

Tilera has had chips and limited systems available for evaluation. The latest crop of chips and systems make it easier for designers to check out the chips and quickly develop platforms based on Tilera's many core silicon.

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