Electronic Design
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Memory Ordering Flaw Found in Rare Version of RISC-V Hardware

More than a hundred errors related to how programs store and retrieve information from memory have been identified in a hardware design compliant with the RISC-V architecture. The flaw is already under repair and doesn't appear in all RISC-V hardware, but it turns the spotlight back on the uphill battle for open-source chips.

Margaret Martonosi, a professor of computer science at Princeton University, and her colleagues published a paper last week that identified gaps in RISC-V’s memory ordering rules, which define how a processor's operations take turns to access shared memory, ensuring that operations don’t cut the line.

The paper, released at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, warned that the flaws could cause errors in software running on the RISC-V instruction set architecture, which lays out the most basic functions of the chip like memory and logic. But the researchers noted that the errors only affected a high-performance version of RISC-V.

“Incorrect memory access orderings can result in software performing calculations using the wrong values,” Martonosi said in a statement. “These in turn can lead to hard-to-debug software errors that either causes the software to crash or to be vulnerable to security exploits.”

Krste Asanović, the chairman of the RISC-V Foundation, an industry group that supervises the open-source design, said that the memory flaws would be fixed this year in the latest specification. Daniel Lustig, a research scientist at Nvidia and one of the paper’s authors, is overseeing the repairs.

The memory errors are not likely to dampen enthusiasm for RISC-V, at least not much more than the industry's unwillingness to learn new architectures or dive into open-source. But RISC-V, which can be freely used and modified, has clearly intrigued companies looking into custom chips. The RISC-V Foundation includes members like Google, Microsoft, and Oracle, as well as IBM, which drafted the Power architecture.

Arguably, the bugs pale in comparison to RISC-V’s other obstacles. To break into the mainstream, it must entice developers trained on rival technology from Intel and ARM. To make matters worse, few companies appear to be turned off by ARM’s licensing rates. One particularly tricky task may be conveying RISC-V’s benefits.

RISC-V’s hook, supporters say, is that it reduces the massive amounts of money required for developing a custom chip. It allows companies to create chips for a fraction of the cost and with better power consumption and performance than closed architectures. It could also make it easier to integrate custom peripherals.

The architecture was first developed by computer scientists at the University of California, Berkeley, who recently started a company called SiFive to sell platforms that serve as a starting point for custom chips. The start-up is targeting chips for wearables and other Internet of Things devices, as well as data centers.

The errors recently found inside RISC-V hardware are related to how programs read from the same memory. While sharing memory improves efficiency, it depends on the computer’s ability to create memory consistency models, which set ground rules for how programs share the space. The models, however, can be affected by slight changes to the machine level, compiler, and high-level programming language.

These issues with memory models have cropped up before in other designs. The researchers pointed out that similar flaws affected ARM-based processors used in some versions of the Galaxy Nexus and Nexus 6 smartphones. ARM acknowledged the bug in 2011 and resolved the issue with changes to the compiler level of the chips.

To test that the models were accurate in RISC-V, the researchers built a hardware debugging tool called TriCheck, which tests memory consistency by using formal specifications memory ordering rules, also called axioms. In one particular high-performance design, the tool found 144 errant programs out of 1,701 test programs.

Asanović, a professor of electrical engineering and computer science at the University of California-Berkeley, said that RISC-V project is considering input from chip designers to "fill the gaps and the holes and getting a [specification] that everyone can agree on." He added: "The memory model is part of that."

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