Do you remember the Transputer? Inmos introduced it back in the 1980s, when single-processor performance was seemingly going to peak. The initial Transputer had a single 20-MHz, 16-bit processing core with four 20-Mbit/s links. David May, the Transputer's architect, is now the CTO of XMOS Semiconductor, which has just introduced the software-defined XCore (see the figure).
The XCore has many similarities to the Transputer, but with major enhancements. The Transputer line started with a 16-bit version and topped out with a floating-point implementation. The XCore starts with a dual-core, 32-bit processing system, and its quad XLinks run at gigabit/s speeds. (XMOS has not released its rated speed yet.)
Each core has 65 kbytes of RAM for code and data. A ROM boot loader brings in applications from off-chip memory, though flash versions of the chip may be available as well. Also, each core is connected to a local XLink switch. The switch handles communication between cores and services the four external XLinks, including forwarding messages that only pass through the chip.
Each core implements conventional peripherals in software in a fashion similar to the Ubicom SX or the Parallax Propeller (see "Parallax Propeller" at www.electronicdesign.com, ED Online 13329). The I/O ports are mapped to registers. The software toggling bits implement peripherals such as serial ports as necessary.
Software peripherals might be a problem. But the architecture is optimized to address issues such as context switching to the point that a core could handle a pair of 100BaseT Ethernet interfaces. The eight context thread images is one way XMOS has addressed the problem. A thread can wait for a change of state on the pins associated with the soft peripheral and the context switch can be activated on the next instruction, leading to very efficient multithreading.
Software peripherals provide flexibility, but they also add to a designer's list of chores since latency and servicing overhead now come into play. Hardware peripherals would still have these issues. But the magnitude is different, since interrupt routines for the latter usually have much less overhead than their software counterparts.
XMOS will provide a collection of standard software peripherals. Yet programmers can easily create their own using the XC compiler. XC is a superset of C, unlike the Occam language, which was used with the original Transputer. In fact, according to Noel Hurley, vice president of marketing at NMOS, XC is 99% C. The small fraction of added syntactic enhancements addresses the XLink communication system.
The system has a GNU C/C++ toolchain for regular application support. The XC code can be linked in as well. XC will be used for most soft peripheral development. The initial release will be more text-based and function-oriented, but a graphical interface for selecting and configuring software peripherals is on the roadmap. This should be an easy addition given the development tools run on the open-source Eclipse IDE.
Chips will fall into a $1 to $10 price range based upon the number of cores, memory, and performance. Power management enables the chip to be used in mobile applications, and DSP instructions help address multimedia applications. These kinds of applications will likely use one or maybe two chips.
The XMOS approach will let vendors distinguish their products by adding features like the IEEE 1588 Precision Time Protocol to an Ethernet soft peripheral. The chip should give multicore systems like Intellasys' SEAforth some interesting competition (see "Cores That Share Chores," ED Online 12692).