Electronic Design

Packet Switching Chips Set Mark For Density, Efficiency, And Flexibility

Four factors are key in designing new networking boxes: power consumption, density, cost, and scalability. Reducing power consumption means using a minimum number of efficient integrated links and reducing the number of off-chip interfaces. For density, integrate as much bandwidth per device as possible and use very highspeed links. Using chips made with standard but advanced CMOS silicon processes minimizes cost.

And then there's the most important factor, scalability. Use a linear ratio of bandwidth to chips, minimize on-chip memory, and decouple the architecture from serial link speed. Enigma Semiconductor's HybriCore scalable packet switch-fabric chip set, comprising a packet switch and a fabric manager, can help designers achieve these goals.

The chip set targets metro access switches and routers, multiservice provisioning platforms (MSPPs), enterprise routers, and storage platforms. It also promises to deliver the quality of service (QoS) for triple-play (voice, video, and data) that will be the standard delivery mode in the future.

ON THE SET
Unlike its competition, the HybriCore delivers true scalable packet switching across the backplane. Earlier switch fabrics divided the input packets into fixed-length backplane cells, producing massive inefficiencies with wasted time slots. However, the HyrbiCore chip set's byte-aligned packet switching provides 98% switching efficiency. Its switching throughput is fully independent of packet-size distribution.

The set includes the EN6240 fabric manager and the EN6110 switch device. The EN6240 is a 40-Gbit/s full duplex fabric manager that manages the flow of packets to and from four Ethernet front ends (FEs), a single 10-Gbit Ethernet (10GE) port, or 10 1-Gbit Ethernet (1GE) interfaces. The Ethernet connections may be copper or optical.

Communications between the EN6240 and the Ethernet ports is through a traffic manager (TM) or a network processing unit (NPU) with its own DRAM (see the figure). Each user interface to the TM or NPU complies with the SPI 4.2 interface and offers a full 12-Gbit/s+ full duplex interface. Since the traffic manager isn't incorporated on the chip, the chip provides better flexibility than some competitive devices.

The EN6240 transmits 14 high-speed serial outputs to the EN6110 switch and receives 14 high-speed serial inputs from the EN6110. The 14 links use special on-chip high-speed serializer/ deserializer (SERDES) circuits good for speeds from 1 Gbit/s to 12.5 Gbits/s on a single pair of traces.

The SERDES receivers use an "eye opening" decision feedback equalization (DFE) circuit that provides full automatic reflection cancellation. An adaptive transmitter equalization tap updates continuously as the environment changes without interrupting data traffic. An 8B/10B encoder/decoder is available for link synchronization and supervision.

HITTING THE SWITCH
The EN6110 is a non-blocking, single-stage 36- by 36-link crossbar switch. It can handle 36 full duplex high-speed serial links with speeds ranging from 2.5 to 12.5 Gbits/s. It performs crossbar switching of messages to and from fabric managers as well as fabric arbitration to enable efficient scheduling of packet data through the switch fabric.

The aggregate user throughput is up to 288 Gbits/s per chip. This lets the system scale with an aggregate bandwidth of greater than 2 Tbits/s. Also, the EN6110 switches any length packet of cell up to 10 kbytes long. The packet traffic is protected by a cyclic redundancy code (CRC). It supports switch card redundancy of 1 + 1, 1:1, or N + M. And, it can handle unicast, multicast, and broadcast packets.

Designers who need a smaller solution can try the EN6220, which is a scaled-down version of the EN6240. It only features five serial links and two SPI 4.2 links with an effective maximum throughput of 20 Gbits/s.

The EN6240 and EN6110 are sampling now. For pricing information, contact the company.

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