Electronic Design

PHY Chip Processes Sonet OC-192, 10-Gbit/s Ethernet

With both Sonet and Ethernet optical transmission speeds at 10 Gbits/s, semiconductor vendors can now make networking chips that can actually handle both protocols. A good example is the Decathlon device from Paxonet Communications.

Decathlon is a fully integrated physical layer (PHY) IC that makes it efficient to incorporate both 10-Gbit/s Ethernet (10GE) LAN and Sonet OC-192c WAN into switches, routers, and other equipment for enterprise, metro, and ISP networks. It includes the Physical Coding Sub-Layer (PCS), WAN Interface Sub-Layer (WIS), and a rate-matching 10-Gbit/s Media-Independent Interface (XGMII) for direct connection to an IEEE-802.3ae 10GE media access control (MAC) sublayer.

The WIS section fully complies with Telecordia/ITU and includes an OC-192c Sonet/SDH interface with framing, pointer processing, and full overhead processing. The Decathlon operates in three modes: 10Gb/b Ethernet LAN-PHY, OC-192c WAN-PHY, and Sonet/SDH OC-192c path terminator with an external packet over Sonet (POS) engine.

The line interface complies with Optical Internetworking Forum (OIF) SFI-4 (SERDES to Framer Interface Level 4) in OC-192c POS applications (622.08 MHz) and IEEE-802.3ae XSBI (644.53 MHz) for 10GE.LAN and WAN PHY applications. The system side interface complies with IEEE XGMII (156.25 MHz). The chip incorporates Sonet transmit/
receive framers and a 64B/66B encoder/decoder used in Ethernet frame delineation.

Housed in an SBGA package, the Decathlon will begin sampling in the fourth quarter.

Paxonet Communications Inc., 4046 Clipper Ct., Fremont, CA 94538; (510) 770-2277, ext. 200; www.paxonet.com.

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