The PowerPC started out as a RISC challenger to the PC's XC86, developed by Apple, IBM, and Motorola. It lost that race, but it has become a major RISC for ICs, ASSPs, and cores. PowerPCs have a large embedded base in printers, telecom, control, and xDSL.
Initially, PowerPC implementations had built-in debugging capability using the Communications On-chip Processor (COP), developed by IBM. Later debug resources built on COP supported a JTAG/TAP interface using on-chip scan chains to monitor and set instructions, memory, and registers. It included on-chip breakpoint comparators for instruction and data addresses, as well as data values. It also defined tracing. COP was used for a number of PowerPCs, like the 550, the 750, and the RS6000.
Motorola has taken to the PowerPC as a RISC engine for its ICs and ASSPs. These PowerPC implementations have deployed many debug resources, like Background Debug Mode, JTAG/TAP-based debuggers, Nexus, and main-bus-based tracing.
The latest fourth-generation version integrates a PowerPC CPU with a vector engine. It uses an extension of the COP, the Power Port Debug Interface. It meets the Book-E debug standards, which extended the PowerPC for embedded applications.
Book-E defines debug events, which set Debug Exception bits in the Debug Status Register and cause a Debug exception. These events include In-struction Address Compare, Data Address Compare, Trap, Branch Taken, Instruction Complete, Interrupt Taken, Return, and Unconditional (set by the UDE signal).
These events can shift the CPU into the Debug Mode for debugging processing. When a debug event occurs in the Debug Mode, they may cause a debug exception, if enabled, and an interrupt.
On some Motorola implementations, the Trace Mode enables either a single-step trace, or a branch trace that records every branch taken. The CPU can be set to take a soft stop or a hard stop. In the soft stop, the CPU halts after the triggering instruction completes. In the hard stop, the CPU halts on detecting the address match and must be restarted via a reset. There also is a 48-bit clock cycle counter, the RUNN counter, for precise cycle control. It can be set to a count and counts down to zero, where it stops the clocks. It can be triggered by a number of signals and events, including interrupts.
Motorola added a Service bus to debug. Instead of scan chains to access key latches, they're directly addressable via Service Access. Up to 16 bits can be set or reset at the same time for a single Service Register Access. These registers are accessed via a Service Access JTAG command.
IBM has built on the PowerPC base, fielding PPC cores and PPC ASSPs. The cores include the 405 RISC, and the ASSPs include communications engines like the 440 GP, a 32-bit RISC SoC that integrates a 32-bit PPC core with a PCI-X bridge, a DDRAM controller, and a DMA controller. These PPCs incorporate an extension of the Book-E design. Instead of a single Debug Mode, they define four modes:
- Internal Debug Mode—supports ROM monitors.
- External Debug Mode—supports JTAG debuggers (Book-E Internal Debug Mode).
- Debug Wait Mode—supports CPU stop/stepping for JTAG while servicing interrupts.
- Real-Time Trace Mode—supports trigger events for real-time trace.
Debug events trigger a debug operation, which depends on the current Debug Mode. Internal Debug Mode supports setting and reacting to hardware and software breakpoints. The debug events can interrupt normal program flow for a debug monitor, while the programs continue to run.
One debug control is to "Freeze Timers." This can be triggered by the JTAG debug port, or via a bit set in the Debug Control Register 0. Timers can be enabled to run, freeze always, or freeze on a debug event. Freeze enables the code to ignore the time in debug, keeping a semblance of real-time count.
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