Electronic Design
RapidIO Trade Association Spec Pushes 10 Gbit/s

RapidIO Trade Association Spec Pushes 10 Gbit/s

The RapidIO Trade Association recently announced their new technology roadmap. The new Serial RapidIO 10xN set of specifications defines serial lane speeds of 10 Gbit/s and higher. I spoke with Tom Cox, RapidIO Trade Association Executive Director, about the latest direction of RapidIO with the new specification.

Wong: What do the 10xN set of specifications cover?

Cox: Overall the 10xN Specifications will move the protocol to serial lane speed of 10 Gbps and higher supporting individual port speeds that scale beyond 100 Gbps. The RapidIO 10xN specification is in development now and is backward compatible with the RapidIO Gen1 and Gen2 systems that are being deployed in the market today. Initially, the RapidIO 10xN specification will support greater than 10 Gbaud per serial lane with lane widths up to x16, resulting in data rates up to 160 Gbps per port. The RapidIO 10xN set of specifications will also scale to serial lane speeds of 25 Gbps and beyond.

Wong: Do the current specifications address the speeds to be implemented?

Cox: The current specifications use common Logical and Transport layers, and as there are no limitations in the current logical and transport layers. The majority of the 10xN and 25xN work is in the Physical layer, similar to when we added 5G and 6.25G, we developed the layered architecture in 1999, allowing for the standard to keep in lock step with main stream PHY technology.

Wong: Will the next generation take advantage of the standard SERDES and PHYs like the Gen 1 and Gen 2 systems?

Cox: The RapidIO Trade Association has worked with its industry leading members to use standard SERDES and PHY's for 10xN. Using common SERDES and PHY's is a primary requirement for our OEM and Semiconductor members, the 10G KR and the projected development of 25G KR are ideal. The time to market and cost advantages compliment the low latency and efficient reliable data delivery of the RapidIO protocol.

Wong: What level of compatibility and interoperability will there be between the newest and older standards?

Cox: RapidIO has maintained a 100% backward compatible roadmap with the RapidIO Gen1 and Gen2 systems that are being deployed in the market today, as important aspect of preserving the investments made by our Embedded Systems focused eco-system. Embedded Systems have longer production life then Consumer, PC's or Servers. It is not uncommon for 10 year old systems to receive seamless upgrades using multiple generations of RapidIO.

Wong: Most implementations of Serial RapidIO are x4 lanes. What lane widths does the current and new standards support?

Cox: Commonly backplanes are x4 lanes, but RapidIO supports lane widths of x1, x2, x4, x8 and even x16. All serial RapidIO can support these port widths with multiple different widths within the same system. This enables designers to manage cost and power while getting the bandwidth suited to the application.

Wong: What connection distances are addressed within the specification?

Cox: RapidIO as a specification does not define the channel, but we do develop our specifications to support common Embedded Systems applications. As key to supporting these applications, there is a short-reach specification for local interconnect up to 20 cm over two connectors on FR4 and a long-reach specification that will support up to 1m over two connectors on FR4. The designer needs to characterize the channel in their design, RapidIO is used in chip-to-chip, board-to-board and it is not uncommon for RapidIO to be deployed on 30m cables in chassis-to-chassis applications.

Wong: What protocol encoding is employed with the current and new standards?

Cox: The RapidIO Gen 1 and Gen 2 Specifications use standard 8b/10b encoding in the PCS. For the 10xN the protocol efficiency is further improved by the use of industry leading coding scheme that moves from the 25% overhead of 8b/10b encoding to schemes that have less than 5% encoding overhead. The details of which will be released with specification public release.

Wong: What is the plans for technology past RapdIO 10xN?

Cox: RapidIO 10xN is in lock step with projected needs by our OEM's for a 40G backplane era of applications like Advanced LTE. Currently RapidIO revisions 1.3 and 2.2 dominate LTE and defense shipments. We are mapping out a path to 25xN, with 100G backplanes in order to set a long term roadmap to satisfy the real-world needs of future applications.

Wong: What applications does RapidIO target now and what new areas might be addressed using this new technology?

Cox: The new technology roadmap scales the needs of RapidIO customers in the wireless, defense, aerospace, imaging, video and server markets beyond what is implementable in other interconnect protocols and sets the stage for OEMs to develop systems with scalable backplanes. The proliferation of 4G handsets is increasingly putting demand on the wireless network, and OEMs need more distributed coverage in smaller form factors, with more data passing between processing elements all with low power and ultra low latency. Cloud computing demands a scalable, energy efficiency fabric within the data centre, and creating scalable systems with 100 Gbps connections to computing nodes, with ultra low latency to enable high volume financial transactions is key. High volume financial systems gain a competitive edge through having the lowest and most deterministic latency. Our defense and aerospace customers continue to rely on RapidIO for mission-critical systems and increased automation of unmanned vehicles. Other operational equipment is driving the need for RapidIO in these demanding real-time processing applications. RapidIO 10xN, with a path to 25xN, sets a long term roadmap to satisfy the real-world needs of all these applications.

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