Electronic Design

Reference Design Advances Next-Gen Carrier Networks

Zarlink Semiconductor and Vitesse Semiconductor offer a joint reference design that delivers synchronization required by carriers to deliver scalable, higher bandwidth communication services over packet-based networks. Pairing technology based on Zarlink's Synchronous Ethernet system synchronizer with Vitesse's Carrier Ethernet Gigabit PHY, the reference design speeds development time of next-generation network products. The reference design combines Zarlink's ZL30143 Synchronous Ethernet (SyncE) dual channel system synchronizer and Vitesse's VSC8574 Gigabit PHY transceiver. The PHY provides both primary and secondary recovered clock outputs as clock references to the ZL30143 in the synchronous timing system. The reference design meets timing synchronization requirements in accordance with ITU-T Recommendation G.8262 for wireless base stations, radio network controllers, gateways, aggregation and transmission equipment, and routers. For applications requiring IEEE 1588v2 phase and time synchronization, the VSC8574 provides both one-step and two-step time stamping in the physical layer with ±10 ns or better accuracy. VITESSE SEMICONDUCTOR CORP., Camarillo, CA. (800) 848-3773. ZARLINK SEMICONDUCTOR, Ottawa, Canada. (613) 592-0200.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.