The PURESPEED I/O burst-mode receiver (BMR) FPGA reference design, targeting Gigabit passive optical networks (GPONs), employs the company's adaptive input logic block found on its SC and SCM FPGAs to establish stable clock to data timing relationships within the lock times specified in GPON ITU-T G.984.1. The design provides high-performance I/O buffers with dedicated logic to provide seamless parallel source synchronous I/O. Other features include a built-in shift register, DDR/SDR mux/demux logic, and dedicated clock divider circuitry for by-2 and by-4 clock division. The reference design can be downloaded from the company's website. For more details, call LATTICE SEMICONDUCTOR CORP., Hillsboro, OR. (800) 528-8423.
Company: LATTICE SEMICONDUCTOR CORP.
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