Electronic Design

Statistics Engine Tracks Events, Improves Host Performance

Statistics engines keep track of the types of data and other events that move across a network. That way, designers can develop new value-added services and functions for edge routers, broadband access equipment, mulitservice provisioning platforms, and other systems.

Developed by Integrated Device Technology, the Statistics Engine (SE) chip improves system efficiency by offloading the data-collection function from the host CPU, network processor, or ASIC. It uses the LA-1 look-aside interface defined by the Network Processor Forum to simplify its connection to the host processor or ASIC. It also packs dual quad-data-rate (QDR) 18-bit memory interfaces for off-chip data storage.

The SE's 512k 32-bit counters can be used to keep track of a number of events (see the figure). A smaller version includes 256k counters. Designers can configure these counters for 64-bit operation, reducing the number of available counters by 50%, to monitor events that have a high occurrence rate.

Removing the statistics function from the host gives the host more time to focus on compute-intensive functions related to meeting IP-based service requirements, like the transition from IPv4 to IPv6 and the deployment of content-rich services that tie revenue to bandwidth consumption.

The chip's integrated 64-bit arithmetic and logic unit (ALU) can offload up to 800 data-path processor cycles (per 64-bit counter update). This reduces the number of network processor cycles required for statistics gathering by 90%. The internally configurable 64/32-bit ALU permits designers to upgrade legacy 32-bit operations to 64-bit operations without incurring performance penalties.

Coupled with the chip's internal multiport memory cell architecture, the ALU enables the SE to update multiple counters with a novel patent-pending approach called "fire-and-forget." This scheme is considered an atomic operation. It replaces the typical memory Read/Modify/ Write sequence and lets the host processor access and update as many as four counters on every clock cycle.

Reducing the update overhead can improve the memory bandwidth to the external quad-data-rate memories by as much as 87%. The reduced latency also ensures coherency for statistics-gathering operations that require multiple statistics updates every 5 ns, which would be a good match for 10-Gbit systems.

Housed in a 576-ball flip-chip package, the 512k-counter SE chip costs $65 each in 25,000-unit quantities. The 256k-counter version goes for $55 each in similar quantities. Samples are immediately available.

Integrated Device Technology Inc.
www.idt.com

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