It’s not in stores yet, but Freescale Semiconductor hopes its silicon crystal approach to flash memory will address the scaling issues that can be found with current approaches. The continuing demand for nonvolatile storage will likely mean this technology will be employed sooner than later.
The floating-gate approach to NOR flash implementations is vulnerable to extrinsic reliability fallout as scaling increases. Likewise, the processing becomes more complex. Several alternatives to the floating-gate approach exist, including ferroelectric RAM (FRAM), magnetic tunneling junctions in magnetic RAM (MRAM), and phasechange memory (PCM).
Freescale’s approach employs a split-cell gate design that uses silicon nanocrystals as the charge storage medium for a nonvolatile flash memory system. The split-gate approach provides fast read/write times and has a high noise immunity and an efficient layout compared to a floating gate. Freescale has demonstrated the technology with 16- and 32-Mbit NOR arrays using 90-nm technology (Fig. 1). It targets Freescale’s flash microcontroller line.
The split-gate bit cell uses a 2.2-nm select gate oxide (Fig. 2). It consists of thermal bottom oxide, a layer of silicon nanocrystals, and deposited top oxide. Using silicon nanocrystals to hold a charge is a good approach because they tolerate charge loss and are simple to integrate into the production process. The methodology also scales well.
Drive current and the program window affect performance. Optimizing both counterdoping and the well implant processes can significantly improve the drive current. Nanocrystal density and area coverage affect the program window due to the charge storage capacity of the nanocrystals in addition to top-oxide trapup. Creating the nanocrystals is on par with the current processing steps with key variations in gas, pressure, and temperature.
An enhanced coverage process (ECP) was developed to increase area coverage at the expense of nanocrystal size uniformity and sphericity. Freescale’s process creates about 110 nanocrystals/cell. With it, the size of the nanocrystals remains the same, as the process is scaled down so the number is reduced. ECP control is key to improved performance and reliability.
The demonstration chips look to meet even the demanding requirements of automotive applications. They have robust data retention that Freescale estimates to be in excess of 20 years. They also have a fast programming and erase cycle of less than 20 µs/32 bits and 1 ms, respectively. The erase cycle increases to 100 ms near the chips’ end of life. There is also a large programming/ erase voltage window of more than 2.7 V.
The technology won’t be available tomorrow but it is coming, hopefully before existing approaches run out of steam.