Electronic Design

Technology Weeds Out C/C++ Loops For Soft-Core Acceleration

Designers writing C/C++ language code for embedded systems applications can breathe a bit easier. A new technology by Proceler Inc. of Berkeley, Calif., simplifies the partitioning of logic between a system's processor and hardware acceleration.

This technology identifies computationally intensive code blocks, such as loops, that are candidates for acceleration. Its cutting-edge compiler implements those blocks in reconfigurable logic as a soft processor while compiling the remaining code as a standard executable for an embedded processor. Three core elements comprise the tool.

First, its Dynamically Variable In-struction Set Architecture (DVAITA) is a soft instruction set architecture (ISA) that defines a flexible model for building fast, application-specific soft processors. DVAITA is realized by the company's soft microarchitecture, a set of modular, presynthesized components that implement an instruction set as well as dataflow and control elements.

The firm's software platform is the second element. The tool creates application-specific soft cores from C/C++ source code by optimizing the performance of compute-intensive portions of the code. Third, Proceler's application programming interface (API) and run-time interface seamlessly integrate the soft processors on a reconfigurable computing system.

Typically, an ISA abstracts hardware functional units into instructions and storage resources into registers. ISAs that are more complex expose other aspects of the datapath that can be scheduled by the compiler. Such "hard" ISAs require the implementation of the instructions to be fixed at design time and presented to the compiler in the form of a fixed microprocessor datapath implementation.

DVAITA, though, is a "soft" ISA. It can include instructions and components customized to a particular application. Its software platform creates application-specific soft processors directly from the high-level C/C++ source code. This platform identifies the code blocks within the source code that would benefit the most from hardware acceleration in reconfigurable logic. Such blocks might encompass packet processing or other communications-related applications. It applies powerful program analysis, transformation, scheduling, and code generation techniques to these code blocks and configures the DVAITA components necessary to create a soft processor to perform the blocks' functions.

Soft processors are automatically implemented on reconfigurable computer systems (RCSs). An RCS combines a microprocessor with an FPGA or CPLD in a bus-based configuration (see the figure). Or, the RCS can be integrated into one of the new processor architectures known as configurable system-on-a-chip (CSoC) devices.

Currently, Proceler is demonstrating an alpha version of the technology. A beta version is expected this summer. Full product release is scheduled for the fall. For details, visit www.proceler.com.

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