A time triggered protocol (TTP) bus is the architecture of choice for safety-critical environments such as automotive steer-by-wire and brake-by-wire systems. NEC's TINA bus controller chip is compatible with TTTech's TTP-IP C2S protocol. The chip incorporates a two-channel 5-Mbit/s TTP bus controller. The link operates at 40 MHz with an interframe gap under 5 ms. On-chip memory includes 4 kbytes of RAM for the Communication Network Interface (CNI) and 8 kbytes for the Message Descriptor List (MEDL) used for scheduling information.
Sample quantities of the TINA chip are available now for $25. Volume production of automotive-grade products is expected in 2005. It runs on 3.3 V and operates from −40°C to 85°C. A free reference design is available with an NEC V850 microcontroller.