Leuven, Belgium and Eindhoven, the Netherlands: At the International Solid State Circuit Conference, Imec and the Holst Centre demonstrated an ultra-low power 8 bit analog to digital convertor (ADC) consuming only 30fJ energy per conversion step. This world-class figure of merit ADC is especially suited for upcoming low energy radios in the ISM (industrial, scientific and medical) radio bands such as low-energy Bluetooth or IEEE 802.15.6 for body-area networks.
Imec and the Holst Centre realized this ultra-low power ADC with record performance by using a concept that combines a successive approximation (SAR) architecture working completely in the charge domain with an asynchronous controller.
By doing all the charge redistribution passively, the power consumption of the SAR ADC is already reduced compared to conventional SAR ADCs. An asynchronous controller is implemented to further minimize the power consumption and to allow operation on a single external sampling clock. This asynchronous implementation thus has no clock-driven pre-charge phase but instead self-synchronizes the various building blocks to maximize the speed of operation and to minimize the power consumption.
The chip was implemented in a 90nm digital CMOS technology. Measurements on silicon show a power consumption of only 69µW at a sampling rate of 10Msamples/s and a standby power of only 17nW. Since none of the ADC building blocks consumes any static power, the power consumption of the ADC scales linearly with the sampling frequency. Thus, the figure of merit of 30fJ/conversion step is maintained from 10kSamples/s to 10MSamples/s making it the widest power-efficient range published amongst comparable state-of-the-art designs.