Ballast control
The ballasts used in integrated compact fluorescent lamps (CFLs) typically do not require power factor correction (PFC) due to their low power levels. However, as energy savings benefits drive increased volumes for these products in the marketplace, PFC is likely to become mandatory sometime in the near future.
Unfortunately, active PFC requires an additional control IC, inductor, diode, and high-voltage MOSFET in the ballast circuit, significantly increasing cost. A simple passive PFC design has lower cost but increases the lamp current crest factor, which reduces lamp life. This design idea presents an improved passive PFC circuit to provide high power factor along with a simple control circuit that reduces the lamp current crest factor to acceptable levels.
The proposed CFL ballast design has five main sections: an ac input stage, a passive, valley-fill PFC stage, a ballast control stage using International Rectifier’s IR2520D adaptive ballast control IC, a half-bridge inverter, and a resonant output stage (see the figure).
The ac input stage consists of a standard full-wave rectifier bridge (DB1-4) with an LC filter (LF, CF) for electromagnetic interference (EMI) suppression. The half-bridge inverter (RMHS, RMLS, MHS, and MLS) and the resonant output stage that follows are also standard designs
The improved passive valley-fill PFC circuit consists of CVF1-2, DVF1-3, RVF, and CX. (Capacitor CX helps filter the half-bridge inverter switching spikes that appear on the dc bus.) During each half-cycle of the rectified ac input, current through diode DVF2 and resistor RVF charges capacitors CVF1 and CVF2 in series to half of the ac peak voltage each. (RVF serves to reduce current waveform peaks as the capacitors charge.)
When the rectified ac input voltage drops below VPeak/2, the capacitors act essentially in parallel and supply load current to the dc bus until the rectified ac input again exceeds VPeak/2 on the next half-cycle.
This passive valley-fill PFC circuit provides good power factor (>0.9) and low total harmonic distortion, or THD (<30%), but has a major drawback: the dc bus ripple is 50%. If the ballast control circuit’s operating frequency were fixed, the resonant output stage would produce a lamp current that followed the dc bus voltage.
The 50% ripple, then, would cause a very high lamp-current crest factor—ILAMP(peak)/ILAMP(average)—resulting in a reduced lamp life. An additional control circuit, consisting of RFMIN2-3, RBUS1-2, and QFMIN, works together with the ballast control IC to decrease this lamp-current crest factor by modulating the IC’s operating frequency.
The IR2520D has a voltage-controlled oscillator (VCO) with an externally programmable minimum frequency. The voltage on the VCO pin (4) and the value of the resistor connected to the FMIN pin (3) determine the half-bridge inverter switching frequency that the IC produces. (See the IR2520D datasheet at www.irf.com for full details.)
When the dc bus reaches a certain voltage, the voltage on the base of QFMIN from the voltage divider (RBUS1 and RBUS2) exceeds the transistor’s conduction threshold, turning QFMIN on. With QFMIN on, the resistance between the FMIN pin (3) and ground becomes the parallel combination of RFMIN1 and the series RFMIN2 and RFMIN3, which is lower than the RFMIN1 resistance the FMIN pin sees with QFMIN off.
A lower resistance on the FMIN pin provides a higher switching frequency, so when the dc bus is near the peak, the inverter switching frequency is higher than the frequency when the dc bus is at the valley. This frequency increase yields a lower lamp voltage than would have appeared if the frequency were fixed at the valley value. The control circuit thus mitigates the peak lamp current so the crest factor (ILAMP(peak)/ILAMP(average)) will be decreased.
The purpose of RFMIN3 is emitter degeneration for improving linearity. Without RFMIN3, QFMIN turns on quickly when the voltage-on base of QFMIN reaches threshold. This quick turn-on distorts the lamp current shape by increasing the operating frequency too rapidly.
The resulting CFL ballast circuit achieves a high power factor (0.96), low THD (28.5%), and an acceptable lamp crest factor (1.71), compared to a typical CFL ballast, which has a lower power factor (0.56), higher THD (128%), and similar crest factor (1.71). The ballast control method is simple, it uses a small number of low-cost components, and the design satisfies all of the necessary ballast requirements.