Electronic Design

Design For Electromagnetic Compliance In Ethernet Systems

With many appliances transitioning to Internet Protocol (IP) networks, the Ethernet interface finds itself in these products for the first time. This makes electromagnetic compliance (EMC) a challenge. Ethernet’s unshielded twisted pair (UTP) data-transmission cable acts as an antenna. Common-mode noise that leaks to it will show up as conducted or radiated emissions, creating unique electromagnetic interference (EMI) issues.

Another requirement is immunity to transient overvoltage and electrostatic discharge (ESD). The discharge of energy into submicron semiconductors can become destructive, especially in devices moving to 65-nm geometries. Traditional strategies for improving EMI/ESD performance involve discrete components, i.e., chokes, ferrite cores, and transient voltage suppressor (TVS) diodes.

These approaches impact Ethernet signal integrity, especially Gigabit Ethernet. Alternatively, by integrating system-level ESD and active common-mode suppression in one device, designers can address EMC issues early in the design cycle.

For EMI, the requirement has been FCC Class-A certification for enterprise class equipment and FCC Class-B certification for residential equipment, with FCC Class-B limits being 10 dB lower than Class-A. With Ethernet ports moving outside the enterprise, it is imperative to design Ethernet interfaces for FCC Class-B compliance. Addressing EMC issues late in the cycle incurs product re-spins and launch delays.

Emissions affecting Ethernet interfaces are usually due to common-mode noise. Energy has no return path on the cable, leading to the formation of a loop antenna. Imbalances in transmission-line length, capacitance, transmitter circuits, or passive components affect differential to common-mode signals, causing emissions.

In an active common-mode suppression (CMS) circuit, the CMS monitors positive and negative signals on the differential pair and shunts common-mode energy to ground by providing low impedance on transmit/receive data (TRD) lines while maintaining high differential impedance (Fig. 1). The TRD signals convert to common mode only at the input of the CMS circuit. This conversion can achieve a matching accuracy of better than 0.1% via current design techniques.

This architecture prevents noise from physical-layer (PHY)/ logic sides on the TRD from getting on the UTP cable. It also prevents noise on the UTP cable from getting to the PHY receiver. And, it improves longitudinal balance of the line while reducing the effects of manufacturing tolerances.

COMMON-MODE SUPPRESSION PERFORMANCE
Adding active common-mode suppression to Ethernet interfaces significantly reduces in-band common-mode noise. Looking at the common-mode rejection ratio (CMRR), Figure 2a shows a test setup and Figure 2b the CMRR test results. Figure 3 shows the in-circuit reduction of commonmode noise. From figure 2b and Figure 3, we see a nominal 15-dB improvement across the transmission band.

The removal of in-band common-mode noise is critical for high EMI performance since the FCC EMI compliance mask is lowest from 30 to 230 MHz. Filtering inband noise requires distinguishing between differential data and common-mode noise signals. If necessary, out-of band-noise is suppressible using small ferrite beads.

TRANSIENT THREATS, SOLUTIONS
Silicon devices need protection from overvoltage and overcurrent conditions caused by external inductive coupling or human body discharges. One issue, cable-disconnect discharge, is a new problem resulting from delivery of power over Ethernet (PoE) cable.

Designers must additionally consider cable discharge events (CDEs) caused by charges building up on the cables when pulling them through conduits. The discharge occurs when plugging cables into equipment, enabling a discharge path to earth ground.

A transient overvoltage protection device has two critical requirements. First, it must turn on faster than the device it protects. Second, it must be able to withstand large transient currents.

In an output ESD structure, design hardening and layout techniques significantly reduce inductive and capacitive effects on the output. A low-inductance diode is critical to achieve fast turn-on times. The design uses ferrite beads, less than 35 nH, between the suppressor and the Ethernet PHY. They help direct ESD through the suppressor and prevent ESD flow through the PHY.

The suppressor provides a higher level of ESD protection than CMOS solutions. Test data shows IEC61000-4-2 air discharge performance beyond ±25 kV, contact discharge of +12 kV, cable discharge equivalent performance greater than ±12 kV, and IEC61000-4-4 and 4-5 performance of 2 kV each for fast transient burst and surge.

ETHERNET SIGNAL INTEGRITY
Careful deployment of the EMI/ESD suppressor ensures no signal degradation. The ferrite beads between suppressor and PHY provide a tuning capability to meet performance requirements over a range of Ethernet transformers and PHYs. They also provide filtering for out-of-band clock tones and direct all ESD through the suppressor. And, the CMS circuit can correct for any differential imbalances in the beads, similar to correcting for transformer or other passive-component imbalances.

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