Designer Limbo—How Low Do Soft Errors Go?

How low can a neutron particle get? Or, more accurately, does the soft error phenomenon occur at ground level?

At the core of this question is the continuing debate about soft errors, those unseen invaders of SRAMs that descend from the high atmosphere and pass through a chip, change the charge stored in a nearby transistor thereby causing a soft error. There is no physical damage involved, but the chip temporarily contains erroneous data.

Where do these space invaders come from? Well, neutron particles or background radiation are generated from cosmic rays or from residual radioactive atoms, such as radium and thorium, that are present in microscopic quantities in many materials. It is this background radiation consisting of neutrons and alpha particles that can pass through semiconductor material.

But this stuff has been around since transistors were invented. So why are soft errors suddenly much more of a discussion topic? To get at the real answer to this, let's put to one side an issue that is currently under debate about error causing neutron particles and that is the 'how low can they go' question? For years, manufacturers of semiconductor devices that needed to operate at very high altitudes where aware of the threat of neutron particles.

However, there was not the same threat for SRAM technology being used at ground level because the chance of soft error at that very low altitude wasn't even seen as a reality. After all most of the cosmic ray particles entering Earth's atmosphere have already lost energy because of atmospheric collisions. And even if they did make it all the way down to ground level electronic systems containing vulnerable SRAM technology, the chances are that they would pass through an inactive section of circuitry and no harm would be done. We on the ground were safe from the chip invaders.

Sadly, we had reckoned without Mr Moore and the inevitable reduction of transistor size that is the keystone of his Law. It is these shrinking transistors in embedded SRAMs that are becoming increasingly vulnerable to soft error. And this is compounded by the trend where the amount of embedded SRAM in chips is increasing exponentially, simply because storing program code and data in embedded SRAM results in SoCs with higher performance. The problem is that because transistors are shrinking, the amount of electric charge to control their operation is also reduced. The result is they are more vulnerable, more sensitive to ionising radiation. In older technology, the transistors where large enough to withstand the effects of this radiation, but for the 120nm newcomers and the even smaller future generations, radiation interference is a real threat.

So that's why soft error at ground level has become such a talking point in the industry. But the real point is how the industry is going to find a way round it. One company, ST Microelectronics, is making good progress in that area and has dramatically reduced the chances of soft error occurring in its SRAM technology by adding capacitors that are integrated into the SRAM memory cell. These increase the amount of charge needed to flip a memory cell so it will take more of a disruption than a depleted ground level neutron to create a data error.

In the meantime, the debate on how disruptive neutron particles are at ground level will rumble on. And finding the answer is not going to be easy. For instance, what is ground level? This in itself is a tremendous variable when looked at in relation to sea level. So beware those of you thinking about using your laptop way up in Lhasa, Tibet, Cuzco or Peru, or even Madrid at a modest 700 metres above the Costa levels – your chances of a system soft error could become higher as well.

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